Version 5.0 Build 148 04/26/2005 SJ Full Version
10
731
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VRSM_ON
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# entity
freedev_cycloneII_50_top
# case_insensitive
# source_file
freedev_cycloneII_50_top.bdf
1155289433
23
# storage
db|freedev_cycloneII_50.(0).cnf
db|freedev_cycloneII_50.(0).cnf
# hierarchies {
|
}
# end
# entity
freedev_cycloneII_50
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage
db|freedev_cycloneII_50.(1).cnf
db|freedev_cycloneII_50.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst
}
# end
# entity
asmi_asmi_control_port_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage
db|freedev_cycloneII_50.(2).cnf
db|freedev_cycloneII_50.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port
}
# end
# entity
asmi
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1155288837
7
# storage
db|freedev_cycloneII_50.(3).cnf
db|freedev_cycloneII_50.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|asmi:the_asmi
}
# end
# entity
asmi_sub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1155288837
7
# storage
db|freedev_cycloneII_50.(4).cnf
db|freedev_cycloneII_50.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|asmi:the_asmi|asmi_sub:the_asmi_sub
}
# end
# entity
tornado_asmi_atom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1155288837
7
# storage
db|freedev_cycloneII_50.(5).cnf
db|freedev_cycloneII_50.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|asmi:the_asmi|tornado_asmi_atom:the_tornado_asmi_atom
}
# end
# entity
cpu_0_data_master_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage
db|freedev_cycloneII_50.(6).cnf
db|freedev_cycloneII_50.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master
}
# end
# entity
cpu_0_instruction_master_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage
db|freedev_cycloneII_50.(7).cnf
db|freedev_cycloneII_50.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master
}
# end
# entity
cpu_0
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
1155288830
7
# storage
db|freedev_cycloneII_50.(8).cnf
db|freedev_cycloneII_50.(8).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|cpu_0:the_cpu_0
}
# end
# entity
cpu_0_test_bench
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_test_bench.v
1155288828
7
# storage
db|freedev_cycloneII_50.(9).cnf
db|freedev_cycloneII_50.(9).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench
}
# end
# entity
cpu_0_rf_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
1155288830
7
# storage
db|freedev_cycloneII_50.(10).cnf
db|freedev_cycloneII_50.(10).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
rf_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
freedev_cycloneII_50:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|freedev_cycloneII_50.(11).cnf
db|freedev_cycloneII_50.(11).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
rf_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_vuo1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
clock0
clock1
clocken0
clocken1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
wren_b
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
freedev_cycloneII_50:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_vuo1
# case_insensitive
# source_file
db|altsyncram_vuo1.tdf
1155289442
6
# storage
db|freedev_cycloneII_50.(12).cnf
db|freedev_cycloneII_50.(12).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
wren_b
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
data_b8
data_b9
data_b10
data_b11
data_b12
data_b13
data_b14
data_b15
data_b16
data_b17
data_b18
data_b19
data_b20
data_b21
data_b22
data_b23
data_b24
data_b25
data_b26
data_b27
data_b28
data_b29
data_b30
data_b31
address_a0
address_a1
address_a2
address_a3
address_a4
address_b0
address_b1
address_b2
address_b3
address_b4
clock0
clock1
clocken0
clocken1
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a20
q_a21
q_a22
q_a23
q_a24
q_a25
q_a26
q_a27
q_a28
q_a29
q_a30
q_a31
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
q_b17
q_b18
q_b19
q_b20
q_b21
q_b22
q_b23
q_b24
q_b25
q_b26
q_b27
q_b28
q_b29
q_b30
q_b31
}
# memory_file {
rf_ram.mif
1155288827
}
# hierarchies {
freedev_cycloneII_50:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated
}
# end
# entity
data_RAM_s1_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage
db|freedev_cycloneII_50.(13).cnf
db|freedev_cycloneII_50.(13).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|data_RAM_s1_arbitrator:the_data_RAM_s1
}
# end
# entity
data_RAM
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
data_RAM.v
1155288832
7
# storage
db|freedev_cycloneII_50.(14).cnf
db|freedev_cycloneII_50.(14).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|data_RAM:the_data_RAM
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|freedev_cycloneII_50.(15).cnf
db|freedev_cycloneII_50.(15).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF