AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
4
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
data_RAM.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_ca01
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
byteena_a
byteena_a
byteena_a
byteena_a
clock0
clocken0
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
freedev_cycloneII_50:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_ca01
# case_insensitive
# source_file
db|altsyncram_ca01.tdf
1155289443
6
# storage
db|freedev_cycloneII_50.(16).cnf
db|freedev_cycloneII_50.(16).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
clocken0
byteena_a0
byteena_a1
byteena_a2
byteena_a3
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a20
q_a21
q_a22
q_a23
q_a24
q_a25
q_a26
q_a27
q_a28
q_a29
q_a30
q_a31
}
# memory_file {
data_RAM.hex
1155288832
}
# hierarchies {
freedev_cycloneII_50:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_ca01:auto_generated
}
# end
# entity
firmware_ROM_s1_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage
db|freedev_cycloneII_50.(17).cnf
db|freedev_cycloneII_50.(17).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1
}
# end
# entity
firmware_ROM
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
firmware_ROM.v
1155288831
7
# storage
db|freedev_cycloneII_50.(18).cnf
db|freedev_cycloneII_50.(18).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
freedev_cycloneII_50:inst|firmware_ROM:the_firmware_ROM
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|freedev_cycloneII_50.(19).cnf
db|freedev_cycloneII_50.(19).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
896
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
4
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
firmware_ROM.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_gq01
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
byteena_a
byteena_a
byteena_a
byteena_a
clock0
clocken0
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
freedev_cycloneII_50:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_gq01
# case_insensitive
# source_file
db|altsyncram_gq01.tdf
1155289443
6
# storage
db|freedev_cycloneII_50.(20).cnf
db|freedev_cycloneII_50.(20).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
clocken0
byteena_a0
byteena_a1
byteena_a2
byteena_a3
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a20
q_a21
q_a22
q_a23
q_a24
q_a25
q_a26
q_a27
q_a28
q_a29
q_a30
q_a31
}
# memory_file {
firmware_ROM.hex
1155108512
}
# hierarchies {
freedev_cycloneII_50:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_gq01:auto_generated
}
# end
# entity
jtag_uart_0_avalon_jtag_slave_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
freedev_cycloneII_50.v
1155288846
7
# storage