{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|F_pc\[21\] memory freedev_cycloneII_50:inst\|payload_buffer:the_payload_buffer\|altsyncram:the_altsyncram\|altsyncram_p111:auto_generated\|ram_block1a5~porta_we_reg 48.29 MHz 20.71 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 48.29 MHz between source register \"freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|F_pc\[21\]\" and destination memory \"freedev_cycloneII_50:inst\|payload_buffer:the_payload_buffer\|altsyncram:the_altsyncram\|altsyncram_p111:auto_generated\|ram_block1a5~porta_we_reg\" (period= 20.71 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.436 ns + Longest register memory " "Info: + Longest register to memory delay is 20.436 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|F_pc\[21\] 1 REG LCFF_X25_Y13_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y13_N7; Fanout = 4; REG Node = 'freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|F_pc\[21\]'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] } "NODE_NAME" } "" } } { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 521 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.116 ns) + CELL(0.664 ns) 3.780 ns freedev_cycloneII_50:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_instruction_master_requests_payload_buffer_s1~295 2 COMB LCCOMB_X28_Y13_N30 2 " "Info: 2: + IC(3.116 ns) + CELL(0.664 ns) = 3.780 ns; Loc. = LCCOMB_X28_Y13_N30; Fanout = 2; COMB Node = 'freedev_cycloneII_50:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_instruction_master_requests_payload_buffer_s1~295'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.780 ns" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~295 } "NODE_NAME" } "" } } { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1965 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.664 ns) + CELL(0.664 ns) 7.108 ns freedev_cycloneII_50:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_instruction_master_requests_payload_buffer_s1~299 3 COMB LCCOMB_X24_Y13_N24 39 " "Info: 3: + IC(2.664 ns) + CELL(0.664 ns) = 7.108 ns; Loc. = LCCOMB_X24_Y13_N24; Fanout = 39; COMB Node = 'freedev_cycloneII_50:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_instruction_master_requests_payload_buffer_s1~299'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.328 ns" { freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~295 freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~299 } "NODE_NAME" } "" } } { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1965 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.512 ns) + CELL(0.378 ns) 8.998 ns freedev_cycloneII_50:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_data_master_qualified_request_payload_buffer_s1~163 4 COMB LCCOMB_X23_Y14_N28 2 " "Info: 4: + IC(1.512 ns) + CELL(0.378 ns) = 8.998 ns; Loc. = LCCOMB_X23_Y14_N28; Fanout = 2; COMB Node = 'freedev_cycloneII_50:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_data_master_qualified_request_payload_buffer_s1~163'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.890 ns" { freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~299 freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~163 } "NODE_NAME" } "" } } { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1959 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.809 ns) + CELL(0.636 ns) 13.443 ns freedev_cycloneII_50:inst\|data_RAM_s1_arbitrator:the_data_RAM_s1\|add~312 5 COMB LCCOMB_X24_Y16_N26 3 " "Info: 5: + IC(3.809 ns) + CELL(0.636 ns) = 13.443 ns; Loc. = LCCOMB_X24_Y16_N26; Fanout = 3; COMB Node = 'freedev_cycloneII_50:inst\|data_RAM_s1_arbitrator:the_data_RAM_s1\|add~312'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "4.445 ns" { freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~163 freedev_cycloneII_50:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|add~312 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.874 ns) + CELL(0.636 ns) 15.953 ns freedev_cycloneII_50:inst\|payload_buffer:the_payload_buffer\|altsyncram:the_altsyncram\|altsyncram_p111:auto_generated\|decode_1oa:decode3\|eq_node\[0\] 6 COMB LCCOMB_X23_Y14_N26 16 " "Info: 6: + IC(1.874 ns) + CELL(0.636 ns) = 15.953 ns; Loc. = LCCOMB_X23_Y14_N26; Fanout = 16; COMB Node = 'freedev_cycloneII_50:inst\|payload_buffer:the_payload_buffer\|altsyncram:the_altsyncram\|altsyncram_p111:auto_generated\|decode_1oa:decode3\|eq_node\[0\]'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "2.510 ns" { freedev_cycloneII_50:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|add~312 freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|decode_1oa:decode3|eq_node[0] } "NODE_NAME" } "" } } { "db/decode_1oa.tdf" "" { Text "J:/board/freedev_cycloneII_50/system/db/decode_1oa.tdf" 29 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.099 ns) + CELL(0.384 ns) 20.436 ns freedev_cycloneII_50:inst\|payload_buffer:the_payload_buffer\|altsyncram:the_altsyncram\|altsyncram_p111:auto_generated\|ram_block1a5~porta_we_reg 7 MEM M4K_X13_Y7 1 " "Info: 7: + IC(4.099 ns) + CELL(0.384 ns) = 20.436 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'freedev_cycloneII_50:inst\|payload_buffer:the_payload_buffer\|altsyncram:the_altsyncram\|altsyncram_p111:auto_generated\|ram_block1a5~porta_we_reg'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "4.483 ns" { freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|decode_1oa:decode3|eq_node[0] freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } "NODE_NAME" } "" } } { "db/altsyncram_p111.tdf" "" { Text "J:/board/freedev_cycloneII_50/system/db/altsyncram_p111.tdf" 162 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.362 ns 16.45 % " "Info: Total cell delay = 3.362 ns ( 16.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.074 ns 83.55 % " "Info: Total interconnect delay = 17.074 ns ( 83.55 % )" {  } {  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "20.436 ns" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~295 freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~299 freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~163 freedev_cycloneII_50:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|add~312 freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|decode_1oa:decode3|eq_node[0] freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.436 ns" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~295 freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~299 freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~163 freedev_cycloneII_50:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|add~312 freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|decode_1oa:decode3|eq_node[0] freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } { 0.000ns 3.116ns 2.664ns 1.512ns 3.809ns 1.874ns 4.099ns } { 0.000ns 0.664ns 0.664ns 0.378ns 0.636ns 0.636ns 0.384ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.082 ns - Smallest " "Info: - Smallest clock skew is 0.082 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.231 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 3.231 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK 1 CLK PIN_M22 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M22; Fanout = 1; CLK Node = 'CLK'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { CLK } "NODE_NAME" } "" } } { "freedev_cycloneII_50_top.bdf" "" { Schematic "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf" { { 104 232 400 120 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns CLK~clkctrl 2 COMB CLKCTRL_G7 1645 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G7; Fanout = 1645; COMB Node = 'CLK~clkctrl'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "freedev_cycloneII_50_top.bdf" "" { Schematic "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf" { { 104 232 400 120 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.157 ns) + CELL(0.835 ns) 3.231 ns freedev_cycloneII_50:inst\|payload_buffer:the_payload_buffer\|altsyncram:the_altsyncram\|altsyncram_p111:auto_generated\|ram_block1a5~porta_we_reg 3 MEM M4K_X13_Y7 1 " "Info: 3: + IC(1.157 ns) + CELL(0.835 ns) = 3.231 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'freedev_cycloneII_50:inst\|payload_buffer:the_payload_buffer\|altsyncram:the_altsyncram\|altsyncram_p111:auto_generated\|ram_block1a5~porta_we_reg'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.992 ns" { CLK~clkctrl freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } "NODE_NAME" } "" } } { "db/altsyncram_p111.tdf" "" { Text "J:/board/freedev_cycloneII_50/system/db/altsyncram_p111.tdf" 162 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.935 ns 59.89 % " "Info: Total cell delay = 1.935 ns ( 59.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.296 ns 40.11 % " "Info: Total interconnect delay = 1.296 ns ( 40.11 % )" {  } {  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.231 ns" { CLK CLK~clkctrl freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.231 ns" { CLK CLK~combout CLK~clkctrl freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } { 0.000ns 0.000ns 0.139ns 1.157ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.149 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.149 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK 1 CLK PIN_M22 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M22; Fanout = 1; CLK Node = 'CLK'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { CLK } "NODE_NAME" } "" } } { "freedev_cycloneII_50_top.bdf" "" { Schematic "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf" { { 104 232 400 120 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns CLK~clkctrl 2 COMB CLKCTRL_G7 1645 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G7; Fanout = 1645; COMB Node = 'CLK~clkctrl'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "freedev_cycloneII_50_top.bdf" "" { Schematic "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf" { { 104 232 400 120 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.231 ns) + CELL(0.679 ns) 3.149 ns freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|F_pc\[21\] 3 REG LCFF_X25_Y13_N7 4 " "Info: 3: + IC(1.231 ns) + CELL(0.679 ns) = 3.149 ns; Loc. = LCFF_X25_Y13_N7; Fanout = 4; REG Node = 'freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|F_pc\[21\]'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.910 ns" { CLK~clkctrl freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] } "NODE_NAME" } "" } } { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 521 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 56.49 % " "Info: Total cell delay = 1.779 ns ( 56.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.370 ns 43.51 % " "Info: Total interconnect delay = 1.370 ns ( 43.51 % )" {  } {  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.149 ns" { CLK CLK~clkctrl freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.149 ns" { CLK CLK~combout CLK~clkctrl freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] } { 0.000ns 0.000ns 0.139ns 1.231ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.231 ns" { CLK CLK~clkctrl freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.231 ns" { CLK CLK~combout CLK~clkctrl freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } { 0.000ns 0.000ns 0.139ns 1.157ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } } { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.149 ns" { CLK CLK~clkctrl freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.149 ns" { CLK CLK~combout CLK~clkctrl freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] } { 0.000ns 0.000ns 0.139ns 1.231ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 521 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_p111.tdf" "" { Text "J:/board/freedev_cycloneII_50/system/db/altsyncram_p111.tdf" 162 2 0 } }  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "20.436 ns" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~295 freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~299 freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~163 freedev_cycloneII_50:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|add~312 freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|decode_1oa:decode3|eq_node[0] freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.436 ns" { freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~295 freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~299 freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~163 freedev_cycloneII_50:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|add~312 freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|decode_1oa:decode3|eq_node[0] freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } { 0.000ns 3.116ns 2.664ns 1.512ns 3.809ns 1.874ns 4.099ns } { 0.000ns 0.664ns 0.664ns 0.378ns 0.636ns 0.636ns 0.384ns } } } { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.231 ns" { CLK CLK~clkctrl freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.231 ns" { CLK CLK~combout CLK~clkctrl freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ram_block1a5~porta_we_reg } { 0.000ns 0.000ns 0.139ns 1.157ns } { 0.000ns 1.100ns 0.000ns 0.835ns } } } { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.149 ns" { CLK CLK~clkctrl freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.149 ns" { CLK CLK~combout CLK~clkctrl freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] } { 0.000ns 0.000ns 0.139ns 1.231ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 124.22 MHz 8.05 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 124.22 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate\" (period= 8.05 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.756 ns + Longest register register " "Info: + Longest register to register delay is 3.756 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LCFF_X9_Y18_N31 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y18_N31; Fanout = 10; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.853 ns) + CELL(0.664 ns) 1.517 ns freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|always0~53 2 COMB LCCOMB_X10_Y18_N26 4 " "Info: 2: + IC(0.853 ns) + CELL(0.664 ns) = 1.517 ns; Loc. = LCCOMB_X10_Y18_N26; Fanout = 4; COMB Node = 'freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|always0~53'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.517 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.401 ns) + CELL(0.636 ns) 2.554 ns freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate~0 3 COMB LCCOMB_X10_Y18_N14 1 " "Info: 3: + IC(0.401 ns) + CELL(0.636 ns) = 2.554 ns; Loc. = LCCOMB_X10_Y18_N14; Fanout = 1; COMB Node = 'freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate~0'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.037 ns" { freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.330 ns) + CELL(0.872 ns) 3.756 ns freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 4 REG LCFF_X10_Y18_N17 2 " "Info: 4: + IC(0.330 ns) + CELL(0.872 ns) = 3.756 ns; Loc. = LCFF_X10_Y18_N17; Fanout = 2; REG Node = 'freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.202 ns" { freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.172 ns 57.83 % " "Info: Total cell delay = 2.172 ns ( 57.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.584 ns 42.17 % " "Info: Total interconnect delay = 1.584 ns ( 42.17 % )" {  } {  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.756 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.756 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 0.853ns 0.401ns 0.330ns } { 0.000ns 0.664ns 0.636ns 0.872ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 1.920 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 1.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G2 96 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G2; Fanout = 96; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.241 ns) + CELL(0.679 ns) 1.920 ns freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 3 REG LCFF_X10_Y18_N17 2 " "Info: 3: + IC(1.241 ns) + CELL(0.679 ns) = 1.920 ns; Loc. = LCFF_X10_Y18_N17; Fanout = 2; REG Node = 'freedev_cycloneII_50:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.920 ns" { altera_internal_jtag~TCKUTAPclkctrl freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 35.36 % " "Info: Total cell delay = 0.679 ns ( 35.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.241 ns 64.64 % " "Info: Total interconnect delay = 1.241 ns ( 64.64 % )" {  } {  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.920 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.920 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 0.000ns 1.241ns } { 0.000ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 1.919 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 1.919 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G2 96 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G2; Fanout = 96; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.240 ns) + CELL(0.679 ns) 1.919 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 3 REG LCFF_X9_Y18_N31 10 " "Info: 3: + IC(1.240 ns) + CELL(0.679 ns) = 1.919 ns; Loc. = LCFF_X9_Y18_N31; Fanout = 10; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.919 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 35.38 % " "Info: Total cell delay = 0.679 ns ( 35.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.240 ns 64.62 % " "Info: Total interconnect delay = 1.240 ns ( 64.62 % )" {  } {  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.919 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.919 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 0.000ns 1.240ns } { 0.000ns 0.000ns 0.679ns } } }  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.920 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.920 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 0.000ns 1.241ns } { 0.000ns 0.000ns 0.679ns } } } { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.919 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.919 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 0.000ns 1.240ns } { 0.000ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0}  } { { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "3.756 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.756 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 0.853ns 0.401ns 0.330ns } { 0.000ns 0.664ns 0.636ns 0.872ns } } } { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.920 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.920 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 0.000ns 1.241ns } { 0.000ns 0.000ns 0.679ns } } } { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "1.919 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.919 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 0.000ns 1.240ns } { 0.000ns 0.000ns 0.679ns } } }  } 0}