?? altsyncram_vuo1.tdf
字號:
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 11,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 11,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a12 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 12,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 12,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a13 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 13,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 13,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a14 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 14,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a15 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 15,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a16 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 16,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a17 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 17,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a18 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 18,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a19 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 19,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a20 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 20,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a21 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 21,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a22 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 22,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a23 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 23,
PORT_B_LAST_ADDRESS = 31,
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -