-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L33 is altera_internal_jtag~TDO at JTAG_X1_Y19_N0
A1L33 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L61);

--A1L43 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y19_N0
A1L43 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L61);

--A1L13 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y19_N0
A1L13 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L61);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y19_N0
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L61);


--W1_tri_state_bridge_0_avalon_slave_arb_addend[1] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1] at LCFF_X23_Y13_N25
W1_tri_state_bridge_0_avalon_slave_arb_addend[1] = DFFEAS(W1L251, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--H1_F_pc[25] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[25] at LCFF_X29_Y13_N21
H1_F_pc[25] = AMPP_FUNCTION(A1L24, H1L016, H1L669, E1L4, H1L616, H1L516, H1_W_valid);


--H1_i_read is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|i_read at LCFF_X28_Y13_N25
H1_i_read = AMPP_FUNCTION(A1L24, H1_i_read_nxt, E1L4);


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] at LCFF_X23_Y13_N1
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  , W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0],  ,  , VCC);


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] at LCFF_X22_Y12_N3
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L72 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~57 at LCCOMB_X23_Y13_N0
W1L72 = H1_F_pc[25] & !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] & !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & !H1_i_read;


--W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable at LCFF_X20_Y17_N21
W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable = DFFEAS(W1L661, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 at LCFF_X20_Y17_N25
W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 = DFFEAS(W1L88, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--H1_W_alu_result[27] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[27] at LCFF_X28_Y16_N5
H1_W_alu_result[27] = AMPP_FUNCTION(A1L24, H1L667, H1_E_shift_rot_result[27], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_d_read is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|d_read at LCFF_X22_Y13_N11
H1_d_read = AMPP_FUNCTION(A1L24, H1_d_read_nxt, E1L4);


--AB1_d_write is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|d_write at LCFF_X24_Y16_N5
AB1_d_write = AMPP_FUNCTION(A1L24, H1_d_write_nxt, E1L4);


--W1_cpu_0_data_master_requests_cfi_flash_0_s1 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1 at LCCOMB_X21_Y14_N4
W1_cpu_0_data_master_requests_cfi_flash_0_s1 = H1_W_alu_result[27] & (AB1_d_write # H1_d_read);


--W1L82 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~58 at LCCOMB_X23_Y13_N4
W1L82 = W1L72 & (!W1_cpu_0_data_master_requests_cfi_flash_0_s1 # !W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 # !W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable);


--W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 at LCFF_X20_Y17_N9
W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 = DFFEAS(W1L09, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L71 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~144 at LCCOMB_X20_Y14_N14
W1L71 = H1_i_read # !W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable # !W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 # !H1_F_pc[25];


--W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] at LCFF_X22_Y13_N9
W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  , W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0],  ,  , VCC);


--W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] at LCFF_X22_Y13_N5
W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(W1L52, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L81 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~145 at LCCOMB_X22_Y13_N8
W1L81 = W1_cpu_0_data_master_requests_cfi_flash_0_s1 & (!W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] & !W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # !H1_d_read);


--H1_d_byteenable[3] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|d_byteenable[3] at LCFF_X25_Y15_N13
H1_d_byteenable[3] = AMPP_FUNCTION(A1L24, H1L691, E1L4);


--H1_d_byteenable[1] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|d_byteenable[1] at LCFF_X25_Y15_N11
H1_d_byteenable[1] = AMPP_FUNCTION(A1L24, H1L491, E1L4);


--J1_cpu_0_data_master_dbs_address[1] is freedev_cycloneII_50:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] at LCFF_X25_Y15_N25
J1_cpu_0_data_master_dbs_address[1] = DFFEAS(J1L5, GLOBAL(A1L24), !GLOBAL(E1L4),  , J1L4,  ,  ,  ,  );


--W1L61 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1[1]~46 at LCCOMB_X23_Y14_N24
W1L61 = J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[3]) # !J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[1];


--H1_d_byteenable[2] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|d_byteenable[2] at LCFF_X25_Y15_N15
H1_d_byteenable[2] = AMPP_FUNCTION(A1L24, H1L591, E1L4);


--H1_d_byteenable[0] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|d_byteenable[0] at LCFF_X25_Y15_N5
H1_d_byteenable[0] = AMPP_FUNCTION(A1L24, H1L791, E1L4);


--W1L51 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1[0]~47 at LCCOMB_X23_Y14_N30
W1L51 = J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[2]) # !J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[0];


--J1_cpu_0_data_master_no_byte_enables_and_last_term is freedev_cycloneII_50:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_no_byte_enables_and_last_term at LCFF_X25_Y15_N19
J1_cpu_0_data_master_no_byte_enables_and_last_term = DFFEAS(J1L631, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L91 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~146 at LCCOMB_X23_Y14_N2
W1L91 = !J1_cpu_0_data_master_no_byte_enables_and_last_term & (W1L61 # W1L51);


--W1L02 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~147 at LCCOMB_X23_Y14_N8
W1L02 = W1L81 & W1L71 & (W1L91 # !AB1_d_write);


--W1_tri_state_bridge_0_avalon_slave_arb_addend[0] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0] at LCFF_X23_Y14_N15
W1_tri_state_bridge_0_avalon_slave_arb_addend[0] = DFFEAS(W1L941, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L19 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_select_n_to_the_cfi_flash_0~0 at LCCOMB_X19_Y13_N0
W1L19 = W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & (W1L02 # W1L82) # !W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !W1_tri_state_bridge_0_avalon_slave_arb_addend[0] & (W1L02 # W1L82);


--E1_data_out is freedev_cycloneII_50:inst|freedev_cycloneII_50_reset_clk_domain_synch_module:freedev_cycloneII_50_reset_clk_domain_synch|data_out at LCFF_X29_Y18_N25
E1_data_out = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L24), GLOBAL(C1L2),  ,  , E1_data_in_d1,  ,  , VCC);


--W1L061 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[0]~58 at LCCOMB_X23_Y13_N26
W1L061 = W1L82 & (W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !W1L02 # !W1_tri_state_bridge_0_avalon_slave_arb_addend[0]);


--W1L161 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~59 at LCCOMB_X23_Y14_N4
W1L161 = W1L02 & (W1_tri_state_bridge_0_avalon_slave_arb_addend[1] # !W1L82 & !W1_tri_state_bridge_0_avalon_slave_arb_addend[0]);


--W1_cfi_flash_0_s1_in_a_read_cycle is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_in_a_read_cycle at LCCOMB_X23_Y14_N18
W1_cfi_flash_0_s1_in_a_read_cycle = W1L061 # W1L161 & H1_d_read;


--W1_cfi_flash_0_s1_wait_counter[3] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[3] at LCFF_X19_Y14_N29
W1_cfi_flash_0_s1_wait_counter[3] = DFFEAS(W1L7, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1_d1_reasons_to_wait is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait at LCFF_X23_Y14_N21
W1_d1_reasons_to_wait = DFFEAS(W1L851, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L551 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_begins_xfer~40 at LCCOMB_X19_Y14_N20
W1L551 = !W1_d1_reasons_to_wait & (W1L82 # W1L02);


--W1L611 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_readn~1 at LCCOMB_X19_Y14_N2
W1L611 = W1_cfi_flash_0_s1_in_a_read_cycle & !W1L551 & !W1_cfi_flash_0_s1_wait_counter[3];


--W1_cfi_flash_0_s1_in_a_write_cycle is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_in_a_write_cycle at LCCOMB_X19_Y14_N14
W1_cfi_flash_0_s1_in_a_write_cycle = !AB1_d_write # !W1L161;


--W1_cfi_flash_0_s1_wait_counter[2] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[2] at LCFF_X19_Y14_N5
W1_cfi_flash_0_s1_wait_counter[2] = DFFEAS(W1L5, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1_cfi_flash_0_s1_wait_counter[1] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[1] at LCFF_X19_Y14_N31
W1_cfi_flash_0_s1_wait_counter[1] = DFFEAS(W1L4, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L711 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_write_n_to_the_cfi_flash_0~106 at LCCOMB_X19_Y14_N18
W1L711 = !W1_cfi_flash_0_s1_wait_counter[1] & !W1_cfi_flash_0_s1_wait_counter[2];


--W1L811 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_write_n_to_the_cfi_flash_0~107 at LCCOMB_X19_Y14_N24
W1L811 = !W1_cfi_flash_0_s1_in_a_write_cycle & !W1L551 & (W1_cfi_flash_0_s1_wait_counter[3] $ !W1L711);


--H1_W_alu_result[24] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[24] at LCFF_X28_Y16_N31
H1_W_alu_result[24] = AMPP_FUNCTION(A1L24, H1L757, H1_E_shift_rot_result[24], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[22] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[22] at LCFF_X28_Y13_N27
H1_F_pc[22] = AMPP_FUNCTION(A1L24, H1L106, H1L069, E1L4, H1L616, H1L516, H1_W_valid);


--W1L511 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[24]~192 at LCCOMB_X27_Y12_N28
W1L511 = W1L161 & (H1_W_alu_result[24]) # !W1L161 & H1_F_pc[22];


--H1_W_alu_result[23] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[23] at LCFF_X27_Y15_N21
H1_W_alu_result[23] = AMPP_FUNCTION(A1L24, H1L457, H1_E_shift_rot_result[23], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[21] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[21] at LCFF_X25_Y13_N7
H1_F_pc[21] = AMPP_FUNCTION(A1L24, H1L895, H1L859, E1L4, H1L616, H1L516, H1_W_valid);


--W1L411 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[23]~193 at LCCOMB_X21_Y13_N6
W1L411 = W1L161 & (H1_W_alu_result[23]) # !W1L161 & H1_F_pc[21];


--H1_W_alu_result[22] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[22] at LCFF_X27_Y15_N1
H1_W_alu_result[22] = AMPP_FUNCTION(A1L24, H1L157, H1_E_shift_rot_result[22], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[20] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[20] at LCFF_X25_Y13_N11
H1_F_pc[20] = AMPP_FUNCTION(A1L24, H1L595, H1L659, E1L4, H1L616, H1L516, H1_W_valid);


--W1L311 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[22]~194 at LCCOMB_X21_Y13_N12
W1L311 = W1L161 & H1_W_alu_result[22] # !W1L161 & (H1_F_pc[20]);


--H1_W_alu_result[21] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[21] at LCFF_X27_Y15_N23
H1_W_alu_result[21] = AMPP_FUNCTION(A1L24, H1L847, H1_E_shift_rot_result[21], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[19] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[19] at LCFF_X25_Y13_N21
H1_F_pc[19] = AMPP_FUNCTION(A1L24, H1L295, H1L459, E1L4, H1L616, H1L516, H1_W_valid);


--W1L211 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[21]~195 at LCCOMB_X21_Y13_N16
W1L211 = W1L161 & H1_W_alu_result[21] # !W1L161 & (H1_F_pc[19]);


--H1_W_alu_result[20] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[20] at LCFF_X27_Y15_N7
H1_W_alu_result[20] = AMPP_FUNCTION(A1L24, H1L547, H1_E_shift_rot_result[20], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[18] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[18] at LCFF_X25_Y13_N13
H1_F_pc[18] = AMPP_FUNCTION(A1L24, H1L985, H1L259, E1L4, H1L616, H1L516, H1_W_valid);


--W1L111 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[20]~196 at LCCOMB_X21_Y13_N14
W1L111 = W1L161 & H1_W_alu_result[20] # !W1L161 & (H1_F_pc[18]);