--H1_W_alu_result[19] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[19] at LCFF_X28_Y16_N25
H1_W_alu_result[19] = AMPP_FUNCTION(A1L24, H1L247, H1_E_shift_rot_result[19], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[17] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[17] at LCFF_X25_Y13_N5
H1_F_pc[17] = AMPP_FUNCTION(A1L24, H1L685, H1L059, E1L4, H1L616, H1L516, H1_W_valid);


--W1L011 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[19]~197 at LCCOMB_X21_Y13_N26
W1L011 = W1L161 & (H1_W_alu_result[19]) # !W1L161 & H1_F_pc[17];


--H1_W_alu_result[18] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[18] at LCFF_X27_Y14_N31
H1_W_alu_result[18] = AMPP_FUNCTION(A1L24, H1L937, H1_E_shift_rot_result[18], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[16] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[16] at LCFF_X25_Y13_N27
H1_F_pc[16] = AMPP_FUNCTION(A1L24, H1L385, H1L849, E1L4, H1L616, H1L516, H1_W_valid);


--W1L901 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[18]~198 at LCCOMB_X21_Y13_N20
W1L901 = W1L161 & (H1_W_alu_result[18]) # !W1L161 & H1_F_pc[16];


--H1_W_alu_result[17] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[17] at LCFF_X27_Y14_N17
H1_W_alu_result[17] = AMPP_FUNCTION(A1L24, H1L637, H1_E_shift_rot_result[17], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[15] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[15] at LCFF_X24_Y14_N19
H1_F_pc[15] = AMPP_FUNCTION(A1L24, H1L085, H1L649, E1L4, H1L616, H1L516, H1_W_valid);


--W1L801 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[17]~199 at LCCOMB_X21_Y13_N2
W1L801 = W1L161 & H1_W_alu_result[17] # !W1L161 & (H1_F_pc[15]);


--H1_W_alu_result[16] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[16] at LCFF_X27_Y14_N25
H1_W_alu_result[16] = AMPP_FUNCTION(A1L24, H1L337, H1_E_shift_rot_result[16], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[14] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[14] at LCFF_X24_Y14_N3
H1_F_pc[14] = AMPP_FUNCTION(A1L24, H1L775, H1L449, E1L4, H1L616, H1L516, H1_W_valid);


--W1L701 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[16]~200 at LCCOMB_X21_Y13_N18
W1L701 = W1L161 & (H1_W_alu_result[16]) # !W1L161 & H1_F_pc[14];


--H1_W_alu_result[15] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[15] at LCFF_X27_Y14_N19
H1_W_alu_result[15] = AMPP_FUNCTION(A1L24, H1L037, H1_E_shift_rot_result[15], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[13] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[13] at LCFF_X25_Y13_N23
H1_F_pc[13] = AMPP_FUNCTION(A1L24, H1L475, H1L249, E1L4, H1L616, H1L516, H1_W_valid);


--W1L601 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[15]~201 at LCCOMB_X25_Y13_N24
W1L601 = W1L161 & (H1_W_alu_result[15]) # !W1L161 & H1_F_pc[13];


--H1_W_alu_result[14] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[14] at LCFF_X27_Y14_N9
H1_W_alu_result[14] = AMPP_FUNCTION(A1L24, H1L727, H1_E_shift_rot_result[14], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[12] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[12] at LCFF_X25_Y13_N9
H1_F_pc[12] = AMPP_FUNCTION(A1L24, H1L175, H1L049, E1L4, H1L616, H1L516, H1_W_valid);


--W1L501 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[14]~202 at LCCOMB_X27_Y14_N12
W1L501 = W1L161 & H1_W_alu_result[14] # !W1L161 & (H1_F_pc[12]);


--H1_W_alu_result[13] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[13] at LCFF_X28_Y16_N11
H1_W_alu_result[13] = AMPP_FUNCTION(A1L24, H1L427, H1_E_shift_rot_result[13], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[11] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[11] at LCFF_X24_Y14_N5
H1_F_pc[11] = AMPP_FUNCTION(A1L24, H1L865, H1L839, E1L4, H1L616, H1L516, H1_W_valid);


--W1L401 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[13]~203 at LCCOMB_X28_Y16_N12
W1L401 = W1L161 & (H1_W_alu_result[13]) # !W1L161 & H1_F_pc[11];


--H1_W_alu_result[12] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[12] at LCFF_X28_Y16_N21
H1_W_alu_result[12] = AMPP_FUNCTION(A1L24, H1L127, H1_E_shift_rot_result[12], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[10] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[10] at LCFF_X24_Y14_N11
H1_F_pc[10] = AMPP_FUNCTION(A1L24, H1L565, H1L639, E1L4, H1L616, H1L516, H1_W_valid);


--W1L301 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[12]~204 at LCCOMB_X24_Y14_N12
W1L301 = W1L161 & H1_W_alu_result[12] # !W1L161 & (H1_F_pc[10]);


--H1_W_alu_result[11] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[11] at LCFF_X27_Y16_N27
H1_W_alu_result[11] = AMPP_FUNCTION(A1L24, H1L817, H1_E_shift_rot_result[11], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[9] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[9] at LCFF_X25_Y14_N5
H1_F_pc[9] = AMPP_FUNCTION(A1L24, H1L265, H1L439, E1L4, H1L616, H1L516, H1_W_valid);


--W1L201 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[11]~205 at LCCOMB_X25_Y14_N18
W1L201 = W1L161 & H1_W_alu_result[11] # !W1L161 & (H1_F_pc[9]);


--H1_W_alu_result[10] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[10] at LCFF_X27_Y16_N29
H1_W_alu_result[10] = AMPP_FUNCTION(A1L24, H1L517, H1_E_shift_rot_result[10], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[8] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[8] at LCFF_X25_Y14_N11
H1_F_pc[8] = AMPP_FUNCTION(A1L24, H1L955, H1L239, E1L4, H1L616, H1L516, H1_W_valid);


--W1L101 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[10]~206 at LCCOMB_X25_Y14_N22
W1L101 = W1L161 & (H1_W_alu_result[10]) # !W1L161 & H1_F_pc[8];


--H1_W_alu_result[9] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[9] at LCFF_X27_Y16_N7
H1_W_alu_result[9] = AMPP_FUNCTION(A1L24, H1L217, H1_E_shift_rot_result[9], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[7] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[7] at LCFF_X27_Y17_N25
H1_F_pc[7] = AMPP_FUNCTION(A1L24, H1L655, H1L039, E1L4, H1L616, H1L516, H1_W_valid);


--W1L001 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[9]~207 at LCCOMB_X27_Y17_N18
W1L001 = W1L161 & (H1_W_alu_result[9]) # !W1L161 & H1_F_pc[7];


--H1_W_alu_result[8] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[8] at LCFF_X27_Y16_N21
H1_W_alu_result[8] = AMPP_FUNCTION(A1L24, H1L907, H1_E_shift_rot_result[8], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[6] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[6] at LCFF_X27_Y17_N17
H1_F_pc[6] = AMPP_FUNCTION(A1L24, H1L355, H1L829, E1L4, H1L616, H1L516, H1_W_valid);


--W1L99 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[8]~208 at LCCOMB_X27_Y17_N4
W1L99 = W1L161 & H1_W_alu_result[8] # !W1L161 & (H1_F_pc[6]);


--H1_W_alu_result[7] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[7] at LCFF_X29_Y17_N25
H1_W_alu_result[7] = AMPP_FUNCTION(A1L24, H1L607, H1_E_shift_rot_result[7], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[5] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[5] at LCFF_X25_Y14_N31
H1_F_pc[5] = AMPP_FUNCTION(A1L24, H1L055, H1L629, E1L4, H1L616, H1L516, H1_W_valid);


--W1L89 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[7]~209 at LCCOMB_X25_Y14_N12
W1L89 = W1L161 & H1_W_alu_result[7] # !W1L161 & (H1_F_pc[5]);


--H1_W_alu_result[6] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[6] at LCFF_X29_Y17_N9
H1_W_alu_result[6] = AMPP_FUNCTION(A1L24, H1L307, H1_E_shift_rot_result[6], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[4] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[4] at LCFF_X25_Y14_N9
H1_F_pc[4] = AMPP_FUNCTION(A1L24, H1L745, H1L429, E1L4, H1L616, H1L516, H1_W_valid);


--W1L79 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[6]~210 at LCCOMB_X25_Y14_N14
W1L79 = W1L161 & H1_W_alu_result[6] # !W1L161 & (H1_F_pc[4]);


--H1_W_alu_result[5] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[5] at LCFF_X25_Y16_N1
H1_W_alu_result[5] = AMPP_FUNCTION(A1L24, H1L007, H1_E_shift_rot_result[5], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[3] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[3] at LCFF_X25_Y16_N13
H1_F_pc[3] = AMPP_FUNCTION(A1L24, H1L316, E1L4, H1_W_valid);


--W1L69 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[5]~211 at LCCOMB_X25_Y16_N30
W1L69 = W1L161 & (H1_W_alu_result[5]) # !W1L161 & H1_F_pc[3];


--H1_W_alu_result[4] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[4] at LCFF_X25_Y18_N15
H1_W_alu_result[4] = AMPP_FUNCTION(A1L24, H1L796, H1_E_shift_rot_result[4], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[2] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[2] at LCFF_X27_Y17_N13
H1_F_pc[2] = AMPP_FUNCTION(A1L24, H1L345, H1L029, E1L4, H1L616, H1L516, H1_W_valid);


--W1L59 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[4]~212 at LCCOMB_X27_Y17_N2
W1L59 = W1L161 & H1_W_alu_result[4] # !W1L161 & (H1_F_pc[2]);


--H1_W_alu_result[3] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[3] at LCFF_X25_Y18_N5
H1_W_alu_result[3] = AMPP_FUNCTION(A1L24, H1L496, H1_E_shift_rot_result[3], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[1] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[1] at LCFF_X27_Y13_N5
H1_F_pc[1] = AMPP_FUNCTION(A1L24, H1L045, H1L819, E1L4, H1L616, H1L516, H1_W_valid);


--W1L49 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[3]~213 at LCCOMB_X25_Y18_N16
W1L49 = W1L161 & H1_W_alu_result[3] # !W1L161 & (H1_F_pc[1]);


--H1_W_alu_result[2] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[2] at LCFF_X25_Y18_N27
H1_W_alu_result[2] = AMPP_FUNCTION(A1L24, H1L196, H1_E_shift_rot_result[2], E1L4, H1L921, H1_R_ctrl_shift_rot);


--H1_F_pc[0] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[0] at LCFF_X27_Y13_N3
H1_F_pc[0] = AMPP_FUNCTION(A1L24, H1L735, H1L619, E1L4, H1L616, H1L516, H1_W_valid);


--W1L39 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[2]~214 at LCCOMB_X24_Y14_N0
W1L39 = W1L161 & H1_W_alu_result[2] # !W1L161 & (H1_F_pc[0]);


--K1_cpu_0_instruction_master_dbs_address[1] is freedev_cycloneII_50:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[1] at LCFF_X20_Y14_N11
K1_cpu_0_instruction_master_dbs_address[1] = DFFEAS(K1L6, GLOBAL(A1L24), !GLOBAL(E1L4),  , K1L4,  ,  ,  ,  );


--W1L29 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[1]~215 at LCCOMB_X24_Y14_N30
W1L29 = W1L161 & (J1_cpu_0_data_master_dbs_address[1]) # !W1L161 & K1_cpu_0_instruction_master_dbs_address[1];


--D1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo at LCFF_X10_Y19_N29
D1_hub_tdo = AMPP_FUNCTION(!A1L23, D1L51, !CC1_state[8], CC1L22);


--W1_cfi_flash_0_s1_wait_counter[0] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[0] at LCFF_X19_Y14_N27
W1_cfi_flash_0_s1_wait_counter[0] = DFFEAS(W1L2, GLOBAL(A1L24), !GLOBAL(E1L4),  ,  ,  ,  ,  ,  );


--W1L911 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|reduce_nor~4 at LCCOMB_X19_Y14_N0
W1L911 = W1_cfi_flash_0_s1_wait_counter[0] # W1_cfi_flash_0_s1_wait_counter[3] # W1_cfi_flash_0_s1_wait_counter[2] # W1_cfi_flash_0_s1_wait_counter[1];


--W1L751 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_end_xfer~30 at LCCOMB_X19_Y14_N6
W1L751 = W1L911 # !W1_d1_reasons_to_wait & (W1L82 # W1L02);


--W1L851 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_end_xfer~31 at LCCOMB_X23_Y14_N20
W1L851 = W1L751 & (W1_cfi_flash_0_s1_in_a_read_cycle # AB1_d_write & W1L161);


--W1L151 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1]~72 at LCCOMB_X23_Y13_N6
W1L151 = W1L161 & (W1L851) # !W1L161 & W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !W1L061;


--W1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] at LCFF_X23_Y13_N27
W1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] = DFFEAS(W1L061, GLOBAL(A1L24), !GLOBAL(E1L4),  , W1L351,  ,  ,  ,  );


--W1L33 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_requests_cfi_flash_0_s1~153 at LCCOMB_X20_Y15_N16
W1L33 = H1_F_pc[25] & !H1_i_read;


--W1L951 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_firsttransfer~84 at LCCOMB_X20_Y14_N12
W1L951 = W1_cpu_0_data_master_requests_cfi_flash_0_s1 & (W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 # W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 & W1L33) # !W1_cpu_0_data_master_requests_cfi_flash_0_s1 & W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 & W1L33;