?? tri_s11.tan.rpt
字號:
Classic Timing Analyzer report for tri_s11
Thu Oct 04 17:06:52 2007
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+---------+-------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+---------+-------------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 12.132 ns ; enaddr2 ; oaddr365[6] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+---------+-------------+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+---------------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+--------------+--------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+--------------+--------------+
; N/A ; None ; 12.132 ns ; enaddr2 ; oaddr365[6] ;
; N/A ; None ; 11.822 ns ; enaddr2 ; oaddr365[7] ;
; N/A ; None ; 11.758 ns ; enaddr2 ; oaddr365[10] ;
; N/A ; None ; 10.921 ns ; enaddr2 ; oaddr365[8] ;
; N/A ; None ; 10.916 ns ; enaddr2 ; oaddr365[1] ;
; N/A ; None ; 9.956 ns ; enaddr2 ; oaddr365[5] ;
; N/A ; None ; 8.411 ns ; enaddr2 ; oaddr365[9] ;
; N/A ; None ; 8.346 ns ; enaddr2 ; oaddr365[2] ;
; N/A ; None ; 7.249 ns ; iaddr365[7] ; oaddr365[7] ;
; N/A ; None ; 7.243 ns ; iaddr365[2] ; oaddr365[2] ;
; N/A ; None ; 7.202 ns ; iaddr365[5] ; oaddr365[5] ;
; N/A ; None ; 6.984 ns ; enaddr2 ; oaddr365[0] ;
; N/A ; None ; 6.972 ns ; enaddr2 ; oaddr365[3] ;
; N/A ; None ; 6.966 ns ; enaddr2 ; oaddr365[4] ;
; N/A ; None ; 6.907 ns ; iaddr365[10] ; oaddr365[10] ;
; N/A ; None ; 6.907 ns ; iaddr365[1] ; oaddr365[1] ;
; N/A ; None ; 6.758 ns ; iaddr365[9] ; oaddr365[9] ;
; N/A ; None ; 6.758 ns ; iaddr365[4] ; oaddr365[4] ;
; N/A ; None ; 6.755 ns ; iaddr365[3] ; oaddr365[3] ;
; N/A ; None ; 6.751 ns ; iaddr365[8] ; oaddr365[8] ;
; N/A ; None ; 6.751 ns ; iaddr365[0] ; oaddr365[0] ;
; N/A ; None ; 6.750 ns ; iaddr365[6] ; oaddr365[6] ;
+-------+-------------------+-----------------+--------------+--------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
Info: Processing started: Thu Oct 04 17:06:51 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tri_s11 -c tri_s11 --timing_analysis_only
Info: Longest tpd from source pin "enaddr2" to destination pin "oaddr365[6]" is 12.132 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_45; Fanout = 11; PIN Node = 'enaddr2'
Info: 2: + IC(9.406 ns) + CELL(1.596 ns) = 12.132 ns; Loc. = PIN_128; Fanout = 0; PIN Node = 'oaddr365[6]'
Info: Total cell delay = 2.726 ns ( 22.47 % )
Info: Total interconnect delay = 9.406 ns ( 77.53 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 112 megabytes of memory during processing
Info: Processing ended: Thu Oct 04 17:06:53 2007
Info: Elapsed time: 00:00:02
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