LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_s8_1 IS
port ( endata3 :IN STD_LOGIC;
	idataDSP : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	odataDSP : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END  tri_s8_1;
ARCHITECTURE bhv OF tri_s8_1 IS
BEGIN
PROCESS(endata3,idataDSP)
BEGIN
IF endata3 = '1' THEN odataDSP <= idataDSP ;
ELSE odataDSP <="ZZZZZZZZ" ; END IF ;
END PROCESS;
END bhv;