?? pxi_dsp_da.map.rpt
字號:
Analysis & Synthesis report for pxi_dsp_da
Thu Oct 11 10:42:33 2007
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis RAM Summary
8. Registers Removed During Synthesis
9. General Register Statistics
10. Source assignments for ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated
11. Source assignments for ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component1|altsyncram:ram_block|altsyncram_5bp1:auto_generated
12. Source assignments for ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated
13. Parameter Settings for User Entity Instance: ram_da:inst6|altsyncram:altsyncram_component
14. Parameter Settings for User Entity Instance: ram2:inst3|alt3pram:alt3pram_component
15. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Oct 11 10:42:32 2007 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; pxi_dsp_da ;
; Top-level Entity Name ; pxi_dsp_da ;
; Family ; Cyclone ;
; Total logic elements ; 23 ;
; Total pins ; 94 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 65,536 ;
; DSP block 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; 0 ;
; Total DLLs ; N/A until Partition Merge ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP1C6Q240C6 ; ;
; Top-level entity name ; pxi_dsp_da ; pxi_dsp_da ;
; Family name ; Cyclone ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; pxi_dsp_da.bdf ; yes ; User Block Diagram/Schematic File ; H:/U2/project/RAM/pxi_dsp_da.bdf ;
; log_ctrl_da.bdf ; yes ; Other ; H:/U2/project/RAM/log_ctrl_da.bdf ;
; CNT12.vhd ; yes ; Other ; H:/U2/project/RAM/CNT12.vhd ;
; ram_da.vhd ; yes ; Other ; H:/U2/project/RAM/ram_da.vhd ;
; altsyncram.tdf ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/lpm_mux.inc ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/lpm_decode.inc ;
; aglobal72.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/aglobal72.inc ;
; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altqpram.inc ;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -