; Analysis & Synthesis Source Files Read                                                                    ;
+----------------------------------+-----------------+-----------------+------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path       ;
+----------------------------------+-----------------+-----------------+------------------------------------+
; cnt12.vhd                        ; yes             ; User VHDL File  ; C:/quartus60/protect/RAM/cnt12.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 0     ;
;     -- Combinational with no register       ; 0     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 0     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 0     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 0     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
; I/O pins                                    ; 17    ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |CNT12                     ; 0 (0)       ; 0            ; 0           ; 17   ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |CNT12              ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; CQI[0..10]                             ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 11 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Thu Oct 04 17:57:06 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CNT12 -c CNT12
Info: Found 2 design units, including 1 entities, in source file cnt12.vhd
    Info: Found design unit 1: CNT12-behav
    Info: Found entity 1: CNT12
Info: Elaborating entity "CNT12" for the top level hierarchy
Warning (14130): Reduced register "CQI[10]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "CQI[9]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "CQI[8]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "CQI[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "CQI[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "CQI[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "CQI[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "CQI[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "CQI[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "CQI[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "CQI[0]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "CQ[0]" stuck at GND
    Warning (13410): Pin "CQ[1]" stuck at GND
    Warning (13410): Pin "CQ[2]" stuck at GND
    Warning (13410): Pin "CQ[3]" stuck at GND
    Warning (13410): Pin "CQ[4]" stuck at GND
    Warning (13410): Pin "CQ[5]" stuck at GND
    Warning (13410): Pin "CQ[6]" stuck at GND
    Warning (13410): Pin "CQ[7]" stuck at GND
    Warning (13410): Pin "CQ[8]" stuck at GND
    Warning (13410): Pin "CQ[9]" stuck at GND
    Warning (13410): Pin "CQ[10]" stuck at GND
    Warning (13410): Pin "C0" stuck at GND
    Warning (13410): Pin "C1" stuck at GND
    Warning (13410): Pin "C2" stuck at GND
Warning: Design contains 3 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "CLK"
    Warning (15610): No output dependent on input pin "RST"
    Warning (15610): No output dependent on input pin "EN"
Info: Implemented 17 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 14 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings
    Info: Allocated 142 megabytes of memory during processing
    Info: Processing ended: Thu Oct 04 17:57:09 2007
    Info: Elapsed time: 00:00:03