|pxi_dsp_da
DA7744_LOAD <= log_ctrl_da:inst7.LOAD
DSP_CLOCK => log_ctrl_da:inst7.clock
DSP_CLOCK => ram_da:inst6.rdclock
DSP_CLOCK1 => CNT12:inst2.CLK
DSP_XF0 => CNT12:inst2.RST
DSP_RST => CNT12:inst2.EN
DA7744_R/W <= log_ctrl_da:inst7./R/W
DA7744_CS <= log_ctrl_da:inst7./CS
ADC7744_DB[0] <= ram_da:inst6.q[0]
ADC7744_DB[1] <= ram_da:inst6.q[1]
ADC7744_DB[2] <= ram_da:inst6.q[2]
ADC7744_DB[3] <= ram_da:inst6.q[3]
ADC7744_DB[4] <= ram_da:inst6.q[4]
ADC7744_DB[5] <= ram_da:inst6.q[5]
ADC7744_DB[6] <= ram_da:inst6.q[6]
ADC7744_DB[7] <= ram_da:inst6.q[7]
ADC7744_DB[8] <= ram_da:inst6.q[8]
ADC7744_DB[9] <= ram_da:inst6.q[9]
ADC7744_DB[10] <= ram_da:inst6.q[10]
ADC7744_DB[11] <= ram_da:inst6.q[11]
ADC7744_DB[12] <= ram_da:inst6.q[12]
ADC7744_DB[13] <= ram_da:inst6.q[13]
ADC7744_DB[14] <= ram_da:inst6.q[14]
ADC7744_DB[15] <= ram_da:inst6.q[15]
Yx2 => ram_da:inst6.wren
Yx2 => ram_da:inst6.wrclock
DSP_DB[0] => ram_da:inst6.data[0]
DSP_DB[1] => ram_da:inst6.data[1]
DSP_DB[2] => ram_da:inst6.data[2]
DSP_DB[3] => ram_da:inst6.data[3]
DSP_DB[4] => ram_da:inst6.data[4]
DSP_DB[5] => ram_da:inst6.data[5]
DSP_DB[6] => ram_da:inst6.data[6]
DSP_DB[7] => ram_da:inst6.data[7]
DSP_DB[8] => ram_da:inst6.data[8]
DSP_DB[9] => ram_da:inst6.data[9]
DSP_DB[10] => ram_da:inst6.data[10]
DSP_DB[11] => ram_da:inst6.data[11]
DSP_DB[12] => ram_da:inst6.data[12]
DSP_DB[13] => ram_da:inst6.data[13]
DSP_DB[14] => ram_da:inst6.data[14]
DSP_DB[15] => ram_da:inst6.data[15]
DSP_AB[0] => ram_da:inst6.wraddress[0]
DSP_AB[0] => ram2:inst3.rdaddress_a[0]
DSP_AB[0] => tri_s11_1:inst5.iaddrDSP[0]
DSP_AB[1] => ram_da:inst6.wraddress[1]
DSP_AB[1] => ram2:inst3.rdaddress_a[1]
DSP_AB[1] => tri_s11_1:inst5.iaddrDSP[1]
DSP_AB[2] => ram_da:inst6.wraddress[2]
DSP_AB[2] => ram2:inst3.rdaddress_a[2]
DSP_AB[2] => tri_s11_1:inst5.iaddrDSP[2]
DSP_AB[3] => ram_da:inst6.wraddress[3]
DSP_AB[3] => ram2:inst3.rdaddress_a[3]
DSP_AB[3] => tri_s11_1:inst5.iaddrDSP[3]
DSP_AB[4] => ram_da:inst6.wraddress[4]
DSP_AB[4] => ram2:inst3.rdaddress_a[4]
DSP_AB[4] => tri_s11_1:inst5.iaddrDSP[4]
DSP_AB[5] => ram_da:inst6.wraddress[5]
DSP_AB[5] => ram2:inst3.rdaddress_a[5]
DSP_AB[5] => tri_s11_1:inst5.iaddrDSP[5]
DSP_AB[6] => ram_da:inst6.wraddress[6]
DSP_AB[6] => ram2:inst3.rdaddress_a[6]
DSP_AB[6] => tri_s11_1:inst5.iaddrDSP[6]
DSP_AB[7] => ram_da:inst6.wraddress[7]
DSP_AB[7] => ram2:inst3.rdaddress_a[7]
DSP_AB[7] => tri_s11_1:inst5.iaddrDSP[7]
DSP_AB[8] => ram_da:inst6.wraddress[8]
DSP_AB[8] => ram2:inst3.rdaddress_a[8]
DSP_AB[8] => tri_s11_1:inst5.iaddrDSP[8]
DSP_AB[9] => ram_da:inst6.wraddress[9]
DSP_AB[9] => ram2:inst3.rdaddress_a[9]
DSP_AB[9] => tri_s11_1:inst5.iaddrDSP[9]
DSP_AB[10] => ram_da:inst6.wraddress[10]
DSP_AB[10] => ram2:inst3.rdaddress_a[10]
DSP_AB[10] => tri_s11_1:inst5.iaddrDSP[10]
CH365_DB[0] <= ram2:inst3.qb[0]
CH365_DB[1] <= ram2:inst3.qb[1]
CH365_DB[2] <= ram2:inst3.qb[2]
CH365_DB[3] <= ram2:inst3.qb[3]
CH365_DB[4] <= ram2:inst3.qb[4]
CH365_DB[5] <= ram2:inst3.qb[5]
CH365_DB[6] <= ram2:inst3.qb[6]
CH365_DB[7] <= ram2:inst3.qb[7]
A13 => log_ctrl_m:inst.A13
A13 => tri_s8:inst10.endata4
A13 => tri_s11:inst8.enaddr2
Yx1 => log_ctrl_m:inst.Yx
Yx1 => tri_s8_1:inst9.endata3
Yx1 => tri_s11_1:inst5.enaddr1
R/W => log_ctrl_m:inst.R/W
MEMW => log_ctrl_m:inst.MEMW
MEMR => log_ctrl_m:inst.MEMR
DSP1_DB[0] <= ram2:inst3.qa[0]
DSP1_DB[1] <= ram2:inst3.qa[1]
DSP1_DB[2] <= ram2:inst3.qa[2]
DSP1_DB[3] <= ram2:inst3.qa[3]
DSP1_DB[4] <= ram2:inst3.qa[4]
DSP1_DB[5] <= ram2:inst3.qa[5]
DSP1_DB[6] <= ram2:inst3.qa[6]
DSP1_DB[7] <= ram2:inst3.qa[7]
CH365[0] => ram2:inst3.rdaddress_b[0]
CH365[1] => ram2:inst3.rdaddress_b[1]
CH365[2] => ram2:inst3.rdaddress_b[2]
CH365[3] => ram2:inst3.rdaddress_b[3]
CH365[4] => ram2:inst3.rdaddress_b[4]
CH365[5] => ram2:inst3.rdaddress_b[5]
CH365[6] => ram2:inst3.rdaddress_b[6]
CH365[7] => ram2:inst3.rdaddress_b[7]
CH365[8] => ram2:inst3.rdaddress_b[8]
CH365[9] => ram2:inst3.rdaddress_b[9]
CH365[10] => ram2:inst3.rdaddress_b[10]
CH365_AB[0] => tri_s11:inst8.iaddr365[0]
CH365_AB[1] => tri_s11:inst8.iaddr365[1]
CH365_AB[2] => tri_s11:inst8.iaddr365[2]
CH365_AB[3] => tri_s11:inst8.iaddr365[3]
CH365_AB[4] => tri_s11:inst8.iaddr365[4]
CH365_AB[5] => tri_s11:inst8.iaddr365[5]
CH365_AB[6] => tri_s11:inst8.iaddr365[6]
CH365_AB[7] => tri_s11:inst8.iaddr365[7]
CH365_AB[8] => tri_s11:inst8.iaddr365[8]
CH365_AB[9] => tri_s11:inst8.iaddr365[9]
CH365_AB[10] => tri_s11:inst8.iaddr365[10]


|pxi_dsp_da|log_ctrl_da:inst7
/CS <= inst2.DB_MAX_OUTPUT_PORT_TYPE
clock => inst2.IN0
C2 => inst.IN0
C1 => inst1.IN0
C0 => inst1.IN1
LOAD <= inst.DB_MAX_OUTPUT_PORT_TYPE
/R/W <= inst2.DB_MAX_OUTPUT_PORT_TYPE


|pxi_dsp_da|CNT12:inst2
CLK => CQI[10].CLK
CLK => CQI[9].CLK
CLK => CQI[8].CLK
CLK => CQI[7].CLK
CLK => CQI[6].CLK
CLK => CQI[5].CLK
CLK => CQI[4].CLK
CLK => CQI[3].CLK
CLK => CQI[2].CLK
CLK => CQI[1].CLK
CLK => CQI[0].CLK
RST => CQI[10].ACLR
RST => CQI[9].ACLR
RST => CQI[8].ACLR
RST => CQI[7].ACLR
RST => CQI[6].ACLR
RST => CQI[5].ACLR
RST => CQI[4].ACLR
RST => CQI[3].ACLR
RST => CQI[2].ACLR
RST => CQI[1].ACLR
RST => CQI[0].ACLR
EN => CQI[10].ENA
EN => CQI[9].ENA
EN => CQI[8].ENA
EN => CQI[7].ENA
EN => CQI[6].ENA
EN => CQI[5].ENA
EN => CQI[4].ENA
EN => CQI[3].ENA
EN => CQI[2].ENA
EN => CQI[1].ENA
EN => CQI[0].ENA
CQ[0] <= CQI[0].DB_MAX_OUTPUT_PORT_TYPE
CQ[1] <= CQI[1].DB_MAX_OUTPUT_PORT_TYPE
CQ[2] <= CQI[2].DB_MAX_OUTPUT_PORT_TYPE
CQ[3] <= CQI[3].DB_MAX_OUTPUT_PORT_TYPE
CQ[4] <= CQI[4].DB_MAX_OUTPUT_PORT_TYPE
CQ[5] <= CQI[5].DB_MAX_OUTPUT_PORT_TYPE
CQ[6] <= CQI[6].DB_MAX_OUTPUT_PORT_TYPE
CQ[7] <= CQI[7].DB_MAX_OUTPUT_PORT_TYPE
CQ[8] <= CQI[8].DB_MAX_OUTPUT_PORT_TYPE
CQ[9] <= CQI[9].DB_MAX_OUTPUT_PORT_TYPE
CQ[10] <= CQI[10].DB_MAX_OUTPUT_PORT_TYPE
C0 <= CQI[0].DB_MAX_OUTPUT_PORT_TYPE
C1 <= CQI[1].DB_MAX_OUTPUT_PORT_TYPE
C2 <= CQI[2].DB_MAX_OUTPUT_PORT_TYPE


|pxi_dsp_da|ram_da:inst6
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
data[8] => altsyncram:altsyncram_component.data_a[8]
data[9] => altsyncram:altsyncram_component.data_a[9]
data[10] => altsyncram:altsyncram_component.data_a[10]
data[11] => altsyncram:altsyncram_component.data_a[11]
data[12] => altsyncram:altsyncram_component.data_a[12]
data[13] => altsyncram:altsyncram_component.data_a[13]
data[14] => altsyncram:altsyncram_component.data_a[14]
data[15] => altsyncram:altsyncram_component.data_a[15]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdaddress[3] => altsyncram:altsyncram_component.address_b[3]
rdaddress[4] => altsyncram:altsyncram_component.address_b[4]
rdaddress[5] => altsyncram:altsyncram_component.address_b[5]
rdaddress[6] => altsyncram:altsyncram_component.address_b[6]
rdaddress[7] => altsyncram:altsyncram_component.address_b[7]
rdaddress[8] => altsyncram:altsyncram_component.address_b[8]
rdaddress[9] => altsyncram:altsyncram_component.address_b[9]
rdaddress[10] => altsyncram:altsyncram_component.address_b[10]
rdclock => altsyncram:altsyncram_component.clock1
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wraddress[3] => altsyncram:altsyncram_component.address_a[3]
wraddress[4] => altsyncram:altsyncram_component.address_a[4]
wraddress[5] => altsyncram:altsyncram_component.address_a[5]
wraddress[6] => altsyncram:altsyncram_component.address_a[6]
wraddress[7] => altsyncram:altsyncram_component.address_a[7]
wraddress[8] => altsyncram:altsyncram_component.address_a[8]
wraddress[9] => altsyncram:altsyncram_component.address_a[9]
wraddress[10] => altsyncram:altsyncram_component.address_a[10]
wrclock => altsyncram:altsyncram_component.clock0
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]
q[8] <= altsyncram:altsyncram_component.q_b[8]
q[9] <= altsyncram:altsyncram_component.q_b[9]
q[10] <= altsyncram:altsyncram_component.q_b[10]
q[11] <= altsyncram:altsyncram_component.q_b[11]
q[12] <= altsyncram:altsyncram_component.q_b[12]
q[13] <= altsyncram:altsyncram_component.q_b[13]
q[14] <= altsyncram:altsyncram_component.q_b[14]
q[15] <= altsyncram:altsyncram_component.q_b[15]


|pxi_dsp_da|ram_da:inst6|altsyncram:altsyncram_component
wren_a => altsyncram_mrg1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_mrg1:auto_generated.data_a[0]
data_a[1] => altsyncram_mrg1:auto_generated.data_a[1]
data_a[2] => altsyncram_mrg1:auto_generated.data_a[2]
data_a[3] => altsyncram_mrg1:auto_generated.data_a[3]
data_a[4] => altsyncram_mrg1:auto_generated.data_a[4]
data_a[5] => altsyncram_mrg1:auto_generated.data_a[5]
data_a[6] => altsyncram_mrg1:auto_generated.data_a[6]
data_a[7] => altsyncram_mrg1:auto_generated.data_a[7]
data_a[8] => altsyncram_mrg1:auto_generated.data_a[8]
data_a[9] => altsyncram_mrg1:auto_generated.data_a[9]
data_a[10] => altsyncram_mrg1:auto_generated.data_a[10]
data_a[11] => altsyncram_mrg1:auto_generated.data_a[11]
data_a[12] => altsyncram_mrg1:auto_generated.data_a[12]
data_a[13] => altsyncram_mrg1:auto_generated.data_a[13]
data_a[14] => altsyncram_mrg1:auto_generated.data_a[14]
data_a[15] => altsyncram_mrg1:auto_generated.data_a[15]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
address_a[0] => altsyncram_mrg1:auto_generated.address_a[0]
address_a[1] => altsyncram_mrg1:auto_generated.address_a[1]
address_a[2] => altsyncram_mrg1:auto_generated.address_a[2]
address_a[3] => altsyncram_mrg1:auto_generated.address_a[3]
address_a[4] => altsyncram_mrg1:auto_generated.address_a[4]
address_a[5] => altsyncram_mrg1:auto_generated.address_a[5]
address_a[6] => altsyncram_mrg1:auto_generated.address_a[6]
address_a[7] => altsyncram_mrg1:auto_generated.address_a[7]
address_a[8] => altsyncram_mrg1:auto_generated.address_a[8]
address_a[9] => altsyncram_mrg1:auto_generated.address_a[9]
address_a[10] => altsyncram_mrg1:auto_generated.address_a[10]
address_b[0] => altsyncram_mrg1:auto_generated.address_b[0]
address_b[1] => altsyncram_mrg1:auto_generated.address_b[1]
address_b[2] => altsyncram_mrg1:auto_generated.address_b[2]
address_b[3] => altsyncram_mrg1:auto_generated.address_b[3]
address_b[4] => altsyncram_mrg1:auto_generated.address_b[4]
address_b[5] => altsyncram_mrg1:auto_generated.address_b[5]
address_b[6] => altsyncram_mrg1:auto_generated.address_b[6]
address_b[7] => altsyncram_mrg1:auto_generated.address_b[7]
address_b[8] => altsyncram_mrg1:auto_generated.address_b[8]
address_b[9] => altsyncram_mrg1:auto_generated.address_b[9]
address_b[10] => altsyncram_mrg1:auto_generated.address_b[10]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_mrg1:auto_generated.clock0
clock1 => altsyncram_mrg1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>