address_b[6] => ram_block1a14.PORTBADDR6
address_b[6] => ram_block1a15.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[7] => ram_block1a8.PORTBADDR7
address_b[7] => ram_block1a9.PORTBADDR7
address_b[7] => ram_block1a10.PORTBADDR7
address_b[7] => ram_block1a11.PORTBADDR7
address_b[7] => ram_block1a12.PORTBADDR7
address_b[7] => ram_block1a13.PORTBADDR7
address_b[7] => ram_block1a14.PORTBADDR7
address_b[7] => ram_block1a15.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[8] => ram_block1a8.PORTBADDR8
address_b[8] => ram_block1a9.PORTBADDR8
address_b[8] => ram_block1a10.PORTBADDR8
address_b[8] => ram_block1a11.PORTBADDR8
address_b[8] => ram_block1a12.PORTBADDR8
address_b[8] => ram_block1a13.PORTBADDR8
address_b[8] => ram_block1a14.PORTBADDR8
address_b[8] => ram_block1a15.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
address_b[9] => ram_block1a8.PORTBADDR9
address_b[9] => ram_block1a9.PORTBADDR9
address_b[9] => ram_block1a10.PORTBADDR9
address_b[9] => ram_block1a11.PORTBADDR9
address_b[9] => ram_block1a12.PORTBADDR9
address_b[9] => ram_block1a13.PORTBADDR9
address_b[9] => ram_block1a14.PORTBADDR9
address_b[9] => ram_block1a15.PORTBADDR9
address_b[10] => ram_block1a0.PORTBADDR10
address_b[10] => ram_block1a1.PORTBADDR10
address_b[10] => ram_block1a2.PORTBADDR10
address_b[10] => ram_block1a3.PORTBADDR10
address_b[10] => ram_block1a4.PORTBADDR10
address_b[10] => ram_block1a5.PORTBADDR10
address_b[10] => ram_block1a6.PORTBADDR10
address_b[10] => ram_block1a7.PORTBADDR10
address_b[10] => ram_block1a8.PORTBADDR10
address_b[10] => ram_block1a9.PORTBADDR10
address_b[10] => ram_block1a10.PORTBADDR10
address_b[10] => ram_block1a11.PORTBADDR10
address_b[10] => ram_block1a12.PORTBADDR10
address_b[10] => ram_block1a13.PORTBADDR10
address_b[10] => ram_block1a14.PORTBADDR10
address_b[10] => ram_block1a15.PORTBADDR10
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
q_b[8] <= ram_block1a8.PORTBDATAOUT
q_b[9] <= ram_block1a9.PORTBDATAOUT
q_b[10] <= ram_block1a10.PORTBDATAOUT
q_b[11] <= ram_block1a11.PORTBDATAOUT
q_b[12] <= ram_block1a12.PORTBDATAOUT
q_b[13] <= ram_block1a13.PORTBDATAOUT
q_b[14] <= ram_block1a14.PORTBDATAOUT
q_b[15] <= ram_block1a15.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a7.ENA0
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a8.ENA0
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a9.ENA0
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a10.ENA0
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a11.ENA0
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a12.ENA0
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a13.ENA0
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a14.ENA0
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a15.ENA0


|pxi_dsp_da|ram2:inst3
data[0] => alt3pram:alt3pram_component.data[0]
data[1] => alt3pram:alt3pram_component.data[1]
data[2] => alt3pram:alt3pram_component.data[2]
data[3] => alt3pram:alt3pram_component.data[3]
data[4] => alt3pram:alt3pram_component.data[4]
data[5] => alt3pram:alt3pram_component.data[5]
data[6] => alt3pram:alt3pram_component.data[6]
data[7] => alt3pram:alt3pram_component.data[7]
rdaddress_a[0] => alt3pram:alt3pram_component.rdaddress_a[0]
rdaddress_a[1] => alt3pram:alt3pram_component.rdaddress_a[1]
rdaddress_a[2] => alt3pram:alt3pram_component.rdaddress_a[2]
rdaddress_a[3] => alt3pram:alt3pram_component.rdaddress_a[3]
rdaddress_a[4] => alt3pram:alt3pram_component.rdaddress_a[4]
rdaddress_a[5] => alt3pram:alt3pram_component.rdaddress_a[5]
rdaddress_a[6] => alt3pram:alt3pram_component.rdaddress_a[6]
rdaddress_a[7] => alt3pram:alt3pram_component.rdaddress_a[7]
rdaddress_a[8] => alt3pram:alt3pram_component.rdaddress_a[8]
rdaddress_a[9] => alt3pram:alt3pram_component.rdaddress_a[9]
rdaddress_a[10] => alt3pram:alt3pram_component.rdaddress_a[10]
rdaddress_b[0] => alt3pram:alt3pram_component.rdaddress_b[0]
rdaddress_b[1] => alt3pram:alt3pram_component.rdaddress_b[1]
rdaddress_b[2] => alt3pram:alt3pram_component.rdaddress_b[2]
rdaddress_b[3] => alt3pram:alt3pram_component.rdaddress_b[3]
rdaddress_b[4] => alt3pram:alt3pram_component.rdaddress_b[4]
rdaddress_b[5] => alt3pram:alt3pram_component.rdaddress_b[5]
rdaddress_b[6] => alt3pram:alt3pram_component.rdaddress_b[6]
rdaddress_b[7] => alt3pram:alt3pram_component.rdaddress_b[7]
rdaddress_b[8] => alt3pram:alt3pram_component.rdaddress_b[8]
rdaddress_b[9] => alt3pram:alt3pram_component.rdaddress_b[9]
rdaddress_b[10] => alt3pram:alt3pram_component.rdaddress_b[10]
rdclock => alt3pram:alt3pram_component.outclock
rden_a => alt3pram:alt3pram_component.rden_a
rden_b => alt3pram:alt3pram_component.rden_b
wraddress[0] => alt3pram:alt3pram_component.wraddress[0]
wraddress[1] => alt3pram:alt3pram_component.wraddress[1]
wraddress[2] => alt3pram:alt3pram_component.wraddress[2]
wraddress[3] => alt3pram:alt3pram_component.wraddress[3]
wraddress[4] => alt3pram:alt3pram_component.wraddress[4]
wraddress[5] => alt3pram:alt3pram_component.wraddress[5]
wraddress[6] => alt3pram:alt3pram_component.wraddress[6]
wraddress[7] => alt3pram:alt3pram_component.wraddress[7]
wraddress[8] => alt3pram:alt3pram_component.wraddress[8]
wraddress[9] => alt3pram:alt3pram_component.wraddress[9]
wraddress[10] => alt3pram:alt3pram_component.wraddress[10]
wrclock => alt3pram:alt3pram_component.inclock
wren => alt3pram:alt3pram_component.wren
qa[0] <= alt3pram:alt3pram_component.qa[0]
qa[1] <= alt3pram:alt3pram_component.qa[1]
qa[2] <= alt3pram:alt3pram_component.qa[2]
qa[3] <= alt3pram:alt3pram_component.qa[3]
qa[4] <= alt3pram:alt3pram_component.qa[4]
qa[5] <= alt3pram:alt3pram_component.qa[5]
qa[6] <= alt3pram:alt3pram_component.qa[6]
qa[7] <= alt3pram:alt3pram_component.qa[7]
qb[0] <= alt3pram:alt3pram_component.qb[0]
qb[1] <= alt3pram:alt3pram_component.qb[1]
qb[2] <= alt3pram:alt3pram_component.qb[2]
qb[3] <= alt3pram:alt3pram_component.qb[3]
qb[4] <= alt3pram:alt3pram_component.qb[4]
qb[5] <= alt3pram:alt3pram_component.qb[5]
qb[6] <= alt3pram:alt3pram_component.qb[6]
qb[7] <= alt3pram:alt3pram_component.qb[7]


|pxi_dsp_da|ram2:inst3|alt3pram:alt3pram_component
wren => altdpram:altdpram_component1.wren
wren => altdpram:altdpram_component2.wren
data[0] => altdpram:altdpram_component1.data[0]
data[0] => altdpram:altdpram_component2.data[0]
data[1] => altdpram:altdpram_component1.data[1]
data[1] => altdpram:altdpram_component2.data[1]
data[2] => altdpram:altdpram_component1.data[2]
data[2] => altdpram:altdpram_component2.data[2]
data[3] => altdpram:altdpram_component1.data[3]
data[3] => altdpram:altdpram_component2.data[3]
data[4] => altdpram:altdpram_component1.data[4]
data[4] => altdpram:altdpram_component2.data[4]
data[5] => altdpram:altdpram_component1.data[5]
data[5] => altdpram:altdpram_component2.data[5]
data[6] => altdpram:altdpram_component1.data[6]
data[6] => altdpram:altdpram_component2.data[6]
data[7] => altdpram:altdpram_component1.data[7]
data[7] => altdpram:altdpram_component2.data[7]
wraddress[0] => altdpram:altdpram_component1.wraddress[0]
wraddress[0] => altdpram:altdpram_component2.wraddress[0]
wraddress[1] => altdpram:altdpram_component1.wraddress[1]
wraddress[1] => altdpram:altdpram_component2.wraddress[1]
wraddress[2] => altdpram:altdpram_component1.wraddress[2]
wraddress[2] => altdpram:altdpram_component2.wraddress[2]
wraddress[3] => altdpram:altdpram_component1.wraddress[3]
wraddress[3] => altdpram:altdpram_component2.wraddress[3]
wraddress[4] => altdpram:altdpram_component1.wraddress[4]
wraddress[4] => altdpram:altdpram_component2.wraddress[4]
wraddress[5] => altdpram:altdpram_component1.wraddress[5]
wraddress[5] => altdpram:altdpram_component2.wraddress[5]
wraddress[6] => altdpram:altdpram_component1.wraddress[6]
wraddress[6] => altdpram:altdpram_component2.wraddress[6]
wraddress[7] => altdpram:altdpram_component1.wraddress[7]
wraddress[7] => altdpram:altdpram_component2.wraddress[7]
wraddress[8] => altdpram:altdpram_component1.wraddress[8]
wraddress[8] => altdpram:altdpram_component2.wraddress[8]
wraddress[9] => altdpram:altdpram_component1.wraddress[9]
wraddress[9] => altdpram:altdpram_component2.wraddress[9]
wraddress[10] => altdpram:altdpram_component1.wraddress[10]
wraddress[10] => altdpram:altdpram_component2.wraddress[10]
inclock => altdpram:altdpram_component1.inclock
inclock => altdpram:altdpram_component2.inclock
inclocken => ~NO_FANOUT~
outclock => altdpram:altdpram_component1.outclock
outclock => altdpram:altdpram_component2.outclock
outclocken => ~NO_FANOUT~
aclr => ~NO_FANOUT~
rden_a => altdpram:altdpram_component1.rden
rden_b => altdpram:altdpram_component2.rden
rdaddress_a[0] => altdpram:altdpram_component1.rdaddress[0]
rdaddress_a[1] => altdpram:altdpram_component1.rdaddress[1]
rdaddress_a[2] => altdpram:altdpram_component1.rdaddress[2]
rdaddress_a[3] => altdpram:altdpram_component1.rdaddress[3]
rdaddress_a[4] => altdpram:altdpram_component1.rdaddress[4]
rdaddress_a[5] => altdpram:altdpram_component1.rdaddress[5]
rdaddress_a[6] => altdpram:altdpram_component1.rdaddress[6]
rdaddress_a[7] => altdpram:altdpram_component1.rdaddress[7]
rdaddress_a[8] => altdpram:altdpram_component1.rdaddress[8]
rdaddress_a[9] => altdpram:altdpram_component1.rdaddress[9]
rdaddress_a[10] => altdpram:altdpram_component1.rdaddress[10]
rdaddress_b[0] => altdpram:altdpram_component2.rdaddress[0]
rdaddress_b[1] => altdpram:altdpram_component2.rdaddress[1]
rdaddress_b[2] => altdpram:altdpram_component2.rdaddress[2]
rdaddress_b[3] => altdpram:altdpram_component2.rdaddress[3]
rdaddress_b[4] => altdpram:altdpram_component2.rdaddress[4]
rdaddress_b[5] => altdpram:altdpram_component2.rdaddress[5]
rdaddress_b[6] => altdpram:altdpram_component2.rdaddress[6]
rdaddress_b[7] => altdpram:altdpram_component2.rdaddress[7]
rdaddress_b[8] => altdpram:altdpram_component2.rdaddress[8]
rdaddress_b[9] => altdpram:altdpram_component2.rdaddress[9]
rdaddress_b[10] => altdpram:altdpram_component2.rdaddress[10]
qa[0] <= altdpram:altdpram_component1.q[0]
qa[1] <= altdpram:altdpram_component1.q[1]
qa[2] <= altdpram:altdpram_component1.q[2]
qa[3] <= altdpram:altdpram_component1.q[3]
qa[4] <= altdpram:altdpram_component1.q[4]
qa[5] <= altdpram:altdpram_component1.q[5]
qa[6] <= altdpram:altdpram_component1.q[6]
qa[7] <= altdpram:altdpram_component1.q[7]
qb[0] <= altdpram:altdpram_component2.q[0]
qb[1] <= altdpram:altdpram_component2.q[1]
qb[2] <= altdpram:altdpram_component2.q[2]
qb[3] <= altdpram:altdpram_component2.q[3]
qb[4] <= altdpram:altdpram_component2.q[4]
qb[5] <= altdpram:altdpram_component2.q[5]
qb[6] <= altdpram:altdpram_component2.q[6]
qb[7] <= altdpram:altdpram_component2.q[7]


|pxi_dsp_da|ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component1