data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
rden_b => ram_block1a0.PORTBRE
rden_b => ram_block1a1.PORTBRE
rden_b => ram_block1a2.PORTBRE
rden_b => ram_block1a3.PORTBRE
rden_b => ram_block1a4.PORTBRE
rden_b => ram_block1a5.PORTBRE
rden_b => ram_block1a6.PORTBRE
rden_b => ram_block1a7.PORTBRE
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a7.ENA0


|pxi_dsp_da|ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2
wren => altsyncram:ram_block.wren_a
data[0] => altsyncram:ram_block.data_a[0]
data[1] => altsyncram:ram_block.data_a[1]
data[2] => altsyncram:ram_block.data_a[2]
data[3] => altsyncram:ram_block.data_a[3]
data[4] => altsyncram:ram_block.data_a[4]
data[5] => altsyncram:ram_block.data_a[5]
data[6] => altsyncram:ram_block.data_a[6]
data[7] => altsyncram:ram_block.data_a[7]
wraddress[0] => altsyncram:ram_block.address_a[0]
wraddress[1] => altsyncram:ram_block.address_a[1]
wraddress[2] => altsyncram:ram_block.address_a[2]
wraddress[3] => altsyncram:ram_block.address_a[3]
wraddress[4] => altsyncram:ram_block.address_a[4]
wraddress[5] => altsyncram:ram_block.address_a[5]
wraddress[6] => altsyncram:ram_block.address_a[6]
wraddress[7] => altsyncram:ram_block.address_a[7]
wraddress[8] => altsyncram:ram_block.address_a[8]
wraddress[9] => altsyncram:ram_block.address_a[9]
wraddress[10] => altsyncram:ram_block.address_a[10]
inclock => altsyncram:ram_block.clock0
inclocken => ~NO_FANOUT~
rden => altsyncram:ram_block.rden_b
rdaddress[0] => altsyncram:ram_block.address_b[0]
rdaddress[1] => altsyncram:ram_block.address_b[1]
rdaddress[2] => altsyncram:ram_block.address_b[2]
rdaddress[3] => altsyncram:ram_block.address_b[3]
rdaddress[4] => altsyncram:ram_block.address_b[4]
rdaddress[5] => altsyncram:ram_block.address_b[5]
rdaddress[6] => altsyncram:ram_block.address_b[6]
rdaddress[7] => altsyncram:ram_block.address_b[7]
rdaddress[8] => altsyncram:ram_block.address_b[8]
rdaddress[9] => altsyncram:ram_block.address_b[9]
rdaddress[10] => altsyncram:ram_block.address_b[10]
outclock => altsyncram:ram_block.clock1
outclocken => ~NO_FANOUT~
aclr => ~NO_FANOUT~
byteena[0] => ~NO_FANOUT~
wraddressstall => ~NO_FANOUT~
rdaddressstall => ~NO_FANOUT~
q[0] <= altsyncram:ram_block.q_b[0]
q[1] <= altsyncram:ram_block.q_b[1]
q[2] <= altsyncram:ram_block.q_b[2]
q[3] <= altsyncram:ram_block.q_b[3]
q[4] <= altsyncram:ram_block.q_b[4]
q[5] <= altsyncram:ram_block.q_b[5]
q[6] <= altsyncram:ram_block.q_b[6]
q[7] <= altsyncram:ram_block.q_b[7]


|pxi_dsp_da|ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block
wren_a => altsyncram_5bp1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => altsyncram_5bp1:auto_generated.rden_b
data_a[0] => altsyncram_5bp1:auto_generated.data_a[0]
data_a[1] => altsyncram_5bp1:auto_generated.data_a[1]
data_a[2] => altsyncram_5bp1:auto_generated.data_a[2]
data_a[3] => altsyncram_5bp1:auto_generated.data_a[3]
data_a[4] => altsyncram_5bp1:auto_generated.data_a[4]
data_a[5] => altsyncram_5bp1:auto_generated.data_a[5]
data_a[6] => altsyncram_5bp1:auto_generated.data_a[6]
data_a[7] => altsyncram_5bp1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_5bp1:auto_generated.address_a[0]
address_a[1] => altsyncram_5bp1:auto_generated.address_a[1]
address_a[2] => altsyncram_5bp1:auto_generated.address_a[2]
address_a[3] => altsyncram_5bp1:auto_generated.address_a[3]
address_a[4] => altsyncram_5bp1:auto_generated.address_a[4]
address_a[5] => altsyncram_5bp1:auto_generated.address_a[5]
address_a[6] => altsyncram_5bp1:auto_generated.address_a[6]
address_a[7] => altsyncram_5bp1:auto_generated.address_a[7]
address_a[8] => altsyncram_5bp1:auto_generated.address_a[8]
address_a[9] => altsyncram_5bp1:auto_generated.address_a[9]
address_a[10] => altsyncram_5bp1:auto_generated.address_a[10]
address_b[0] => altsyncram_5bp1:auto_generated.address_b[0]
address_b[1] => altsyncram_5bp1:auto_generated.address_b[1]
address_b[2] => altsyncram_5bp1:auto_generated.address_b[2]
address_b[3] => altsyncram_5bp1:auto_generated.address_b[3]
address_b[4] => altsyncram_5bp1:auto_generated.address_b[4]
address_b[5] => altsyncram_5bp1:auto_generated.address_b[5]
address_b[6] => altsyncram_5bp1:auto_generated.address_b[6]
address_b[7] => altsyncram_5bp1:auto_generated.address_b[7]
address_b[8] => altsyncram_5bp1:auto_generated.address_b[8]
address_b[9] => altsyncram_5bp1:auto_generated.address_b[9]
address_b[10] => altsyncram_5bp1:auto_generated.address_b[10]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_5bp1:auto_generated.clock0
clock1 => altsyncram_5bp1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_5bp1:auto_generated.q_b[0]
q_b[1] <= altsyncram_5bp1:auto_generated.q_b[1]
q_b[2] <= altsyncram_5bp1:auto_generated.q_b[2]
q_b[3] <= altsyncram_5bp1:auto_generated.q_b[3]
q_b[4] <= altsyncram_5bp1:auto_generated.q_b[4]
q_b[5] <= altsyncram_5bp1:auto_generated.q_b[5]
q_b[6] <= altsyncram_5bp1:auto_generated.q_b[6]
q_b[7] <= altsyncram_5bp1:auto_generated.q_b[7]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|pxi_dsp_da|ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_blo