{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Web Edition " "Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 04 11:24:57 2007 " "Info: Processing started: Thu Oct 04 11:24:57 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off tri_s11_1 -c tri_s11_1 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tri_s11_1 -c tri_s11_1 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "enaddr oaddrDSP\[6\] 12.132 ns Longest " "Info: Longest tpd from source pin \"enaddr\" to destination pin \"oaddrDSP\[6\]\" is 12.132 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns enaddr 1 PIN PIN_45 11 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_45; Fanout = 11; PIN Node = 'enaddr'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { enaddr } "NODE_NAME" } } { "tri_s11_1.vhd" "" { Text "C:/quartus60/protect/RAM/tri_s11_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(9.406 ns) + CELL(1.596 ns) 12.132 ns oaddrDSP\[6\] 2 PIN PIN_128 0 " "Info: 2: + IC(9.406 ns) + CELL(1.596 ns) = 12.132 ns; Loc. = PIN_128; Fanout = 0; PIN Node = 'oaddrDSP\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.002 ns" { enaddr oaddrDSP[6] } "NODE_NAME" } } { "tri_s11_1.vhd" "" { Text "C:/quartus60/protect/RAM/tri_s11_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 22.47 % ) " "Info: Total cell delay = 2.726 ns ( 22.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.406 ns ( 77.53 % ) " "Info: Total interconnect delay = 9.406 ns ( 77.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.132 ns" { enaddr oaddrDSP[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.132 ns" { enaddr {} enaddr~out0 {} oaddrDSP[6] {} } { 0.000ns 0.000ns 9.406ns } { 0.000ns 1.130ns 1.596ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 04 11:24:58 2007 " "Info: Processing ended: Thu Oct 04 11:24:58 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}