{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Web Edition " "Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 04 16:31:22 2007 " "Info: Processing started: Thu Oct 04 16:31:22 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off CNT12 -c CNT12 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CNT12 -c CNT12 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "cnt12.vhd" "" { Text "C:/quartus60/protect/RAM/cnt12.vhd" 5 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register CQI\[8\] register CQI\[11\] 282.65 MHz 3.538 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 282.65 MHz between source register \"CQI\[8\]\" and destination register \"CQI\[11\]\" (period= 3.538 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.336 ns + Longest register register " "Info: + Longest register to register delay is 3.336 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CQI\[8\] 1 REG LC_X1_Y16_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y16_N2; Fanout = 5; REG Node = 'CQI\[8\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CQI[8] } "NODE_NAME" } } { "cnt12.vhd" "" { Text "C:/quartus60/protect/RAM/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.952 ns) + CELL(0.340 ns) 1.292 ns LessThan0~129 2 COMB LC_X1_Y17_N2 1 " "Info: 2: + IC(0.952 ns) + CELL(0.340 ns) = 1.292 ns; Loc. = LC_X1_Y17_N2; Fanout = 1; COMB Node = 'LessThan0~129'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.292 ns" { CQI[8] LessThan0~129 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 1.520 ns LessThan0~130 3 COMB LC_X1_Y17_N3 12 " "Info: 3: + IC(0.140 ns) + CELL(0.088 ns) = 1.520 ns; Loc. = LC_X1_Y17_N3; Fanout = 12; COMB Node = 'LessThan0~130'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.228 ns" { LessThan0~129 LessThan0~130 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.960 ns) + CELL(0.856 ns) 3.336 ns CQI\[11\] 4 REG LC_X1_Y16_N5 3 " "Info: 4: + IC(0.960 ns) + CELL(0.856 ns) = 3.336 ns; Loc. = LC_X1_Y16_N5; Fanout = 3; REG Node = 'CQI\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.816 ns" { LessThan0~130 CQI[11] } "NODE_NAME" } } { "cnt12.vhd" "" { Text "C:/quartus60/protect/RAM/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.284 ns ( 38.49 % ) " "Info: Total cell delay = 1.284 ns ( 38.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.052 ns ( 61.51 % ) " "Info: Total interconnect delay = 2.052 ns ( 61.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.336 ns" { CQI[8] LessThan0~129 LessThan0~130 CQI[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.336 ns" { CQI[8] {} LessThan0~129 {} LessThan0~130 {} CQI[11] {} } { 0.000ns 0.952ns 0.140ns 0.960ns } { 0.000ns 0.340ns 0.088ns 0.856ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.271 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_29 12 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 12; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "cnt12.vhd" "" { Text "C:/quartus60/protect/RAM/cnt12.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns CQI\[11\] 2 REG LC_X1_Y16_N5 3 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X1_Y16_N5; Fanout = 3; REG Node = 'CQI\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { CLK CQI[11] } "NODE_NAME" } } { "cnt12.vhd" "" { Text "C:/quartus60/protect/RAM/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.84 % ) " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns ( 26.16 % ) " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK CQI[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK {} CLK~out0 {} CQI[11] {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.271 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_29 12 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 12; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "cnt12.vhd" "" { Text "C:/quartus60/protect/RAM/cnt12.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns CQI\[8\] 2 REG LC_X1_Y16_N2 5 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X1_Y16_N2; Fanout = 5; REG Node = 'CQI\[8\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { CLK CQI[8] } "NODE_NAME" } } { "cnt12.vhd" "" { Text "C:/quartus60/protect/RAM/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.84 % ) " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns ( 26.16 % ) " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK CQI[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK {} CLK~out0 {} CQI[8] {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK CQI[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK {} CLK~out0 {} CQI[11] {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK CQI[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK {} CLK~out0 {} CQI[8] {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "cnt12.vhd" "" { Text "C:/quartus60/protect/RAM/cnt12.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "cnt12.vhd" "" { Text "C:/quartus60/protect/RAM/cnt12.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.336 ns" { CQI[8] LessThan0~129 LessThan0~130 CQI[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.336 ns" { CQI[8] {} LessThan0~129 {} LessThan0~130 {} CQI[11] {} } { 0.000ns 0.952ns 0.140ns 0.960ns } { 0.000ns 0.340ns 0.088ns 0.856ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK CQI[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK {} CLK~out0 {} CQI[11] {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK CQI[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK {} CLK~out0 {} CQI[8] {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}