{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off pxi_dsp_da -c pxi_dsp_da --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pxi_dsp_da -c pxi_dsp_da --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "DSP_CLOCK " "Info: Assuming node \"DSP_CLOCK\" is an undefined clock" {  } { { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { -80 -136 32 -64 "DSP_CLOCK" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DSP_CLOCK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Yx2 " "Info: Assuming node \"Yx2\" is an undefined clock" {  } { { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { 184 -136 32 200 "Yx2" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Yx2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "MEMR " "Info: Assuming node \"MEMR\" is an undefined clock" {  } { { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { 336 -136 32 352 "MEMR" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "MEMR" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "R/W " "Info: Assuming node \"R/W\" is an undefined clock" {  } { { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { 272 -136 32 288 "R/W" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "R/W" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A13 " "Info: Assuming node \"A13\" is an undefined clock" {  } { { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { 208 -136 32 224 "A13" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "A13" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "MEMW " "Info: Assuming node \"MEMW\" is an undefined clock" {  } { { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { 304 -136 32 320 "MEMW" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "MEMW" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Yx1 " "Info: Assuming node \"Yx1\" is an undefined clock" {  } { { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { 240 -136 32 256 "Yx1" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Yx1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}