{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "log_ctrl_m:inst\|inst3 " "Info: Detected gated clock \"log_ctrl_m:inst\|inst3\" as buffer" {  } { { "log_ctrl_m.bdf" "" { Schematic "H:/U2/project/RAM/log_ctrl_m.bdf" { { 160 320 384 208 "inst3" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "log_ctrl_m:inst\|inst3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "log_ctrl_m:inst\|inst4 " "Info: Detected gated clock \"log_ctrl_m:inst\|inst4\" as buffer" {  } { { "log_ctrl_m.bdf" "" { Schematic "H:/U2/project/RAM/log_ctrl_m.bdf" { { 256 232 296 304 "inst4" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "log_ctrl_m:inst\|inst4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "DSP_CLOCK memory ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~portb_address_reg0 memory ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|q_b\[15\] 255.95 MHz 3.907 ns Internal " "Info: Clock \"DSP_CLOCK\" has Internal fmax of 255.95 MHz between source memory \"ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~portb_address_reg0\" and destination memory \"ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|q_b\[15\]\" (period= 3.907 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.323 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~portb_address_reg0 1 MEM M4K_X17_Y4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y4; Fanout = 2; MEM Node = 'ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~portb_address_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 503 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.323 ns) 3.323 ns ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|q_b\[15\] 2 MEM M4K_X17_Y4 1 " "Info: 2: + IC(0.000 ns) + CELL(3.323 ns) = 3.323 ns; Loc. = M4K_X17_Y4; Fanout = 1; MEM Node = 'ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|q_b\[15\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] } "NODE_NAME" } } { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.323 ns ( 100.00 % ) " "Info: Total cell delay = 3.323 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] {} } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns - Smallest " "Info: - Smallest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DSP_CLOCK destination 2.231 ns + Shortest memory " "Info: + Shortest clock path from clock \"DSP_CLOCK\" to destination memory is 2.231 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns DSP_CLOCK 1 CLK PIN_29 106 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 106; CLK Node = 'DSP_CLOCK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DSP_CLOCK } "NODE_NAME" } } { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { -80 -136 32 -64 "DSP_CLOCK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.541 ns) 2.231 ns ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|q_b\[15\] 2 MEM M4K_X17_Y4 1 " "Info: 2: + IC(0.560 ns) + CELL(0.541 ns) = 2.231 ns; Loc. = M4K_X17_Y4; Fanout = 1; MEM Node = 'ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|q_b\[15\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.101 ns" { DSP_CLOCK ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] } "NODE_NAME" } } { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.671 ns ( 74.90 % ) " "Info: Total cell delay = 1.671 ns ( 74.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 25.10 % ) " "Info: Total interconnect delay = 0.560 ns ( 25.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { DSP_CLOCK ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.231 ns" { DSP_CLOCK {} DSP_CLOCK~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.541ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DSP_CLOCK source 2.243 ns - Longest memory " "Info: - Longest clock path from clock \"DSP_CLOCK\" to source memory is 2.243 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns DSP_CLOCK 1 CLK PIN_29 106 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 106; CLK Node = 'DSP_CLOCK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DSP_CLOCK } "NODE_NAME" } } { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { -80 -136 32 -64 "DSP_CLOCK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.553 ns) 2.243 ns ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~portb_address_reg0 2 MEM M4K_X17_Y4 2 " "Info: 2: + IC(0.560 ns) + CELL(0.553 ns) = 2.243 ns; Loc. = M4K_X17_Y4; Fanout = 2; MEM Node = 'ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~portb_address_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.113 ns" { DSP_CLOCK ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 503 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.683 ns ( 75.03 % ) " "Info: Total cell delay = 1.683 ns ( 75.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 24.97 % ) " "Info: Total interconnect delay = 0.560 ns ( 24.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.243 ns" { DSP_CLOCK ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.243 ns" { DSP_CLOCK {} DSP_CLOCK~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.553ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { DSP_CLOCK ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.231 ns" { DSP_CLOCK {} DSP_CLOCK~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.541ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.243 ns" { DSP_CLOCK ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.243 ns" { DSP_CLOCK {} DSP_CLOCK~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.553ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 503 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 34 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] {} } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { DSP_CLOCK ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.231 ns" { DSP_CLOCK {} DSP_CLOCK~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|q_b[15] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.541ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.243 ns" { DSP_CLOCK ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.243 ns" { DSP_CLOCK {} DSP_CLOCK~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~portb_address_reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.553ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}