{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Yx2 memory ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_datain_reg0 memory ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_memory_reg0 256.02 MHz 3.906 ns Internal " "Info: Clock \"Yx2\" has Internal fmax of 256.02 MHz between source memory \"ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_datain_reg0\" and destination memory \"ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_memory_reg0\" (period= 3.906 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.323 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_datain_reg0 1 MEM M4K_X17_Y4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y4; Fanout = 1; MEM Node = 'ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_datain_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 503 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.323 ns) 3.323 ns ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_memory_reg0 2 MEM M4K_X17_Y4 0 " "Info: 2: + IC(0.000 ns) + CELL(3.323 ns) = 3.323 ns; Loc. = M4K_X17_Y4; Fanout = 0; MEM Node = 'ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_memory_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 503 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.323 ns ( 100.00 % ) " "Info: Total cell delay = 3.323 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 {} } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns - Smallest " "Info: - Smallest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Yx2 destination 2.235 ns + Shortest memory " "Info: + Shortest clock path from clock \"Yx2\" to destination memory is 2.235 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Yx2 1 CLK PIN_28 248 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_28; Fanout = 248; CLK Node = 'Yx2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Yx2 } "NODE_NAME" } } { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { 184 -136 32 200 "Yx2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.545 ns) 2.235 ns ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_memory_reg0 2 MEM M4K_X17_Y4 0 " "Info: 2: + IC(0.560 ns) + CELL(0.545 ns) = 2.235 ns; Loc. = M4K_X17_Y4; Fanout = 0; MEM Node = 'ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_memory_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.105 ns" { Yx2 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 503 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.675 ns ( 74.94 % ) " "Info: Total cell delay = 1.675 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.560 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.235 ns" { Yx2 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.235 ns" { Yx2 {} Yx2~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.545ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Yx2 source 2.246 ns - Longest memory " "Info: - Longest clock path from clock \"Yx2\" to source memory is 2.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Yx2 1 CLK PIN_28 248 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_28; Fanout = 248; CLK Node = 'Yx2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Yx2 } "NODE_NAME" } } { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { 184 -136 32 200 "Yx2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.556 ns) 2.246 ns ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_datain_reg0 2 MEM M4K_X17_Y4 1 " "Info: 2: + IC(0.560 ns) + CELL(0.556 ns) = 2.246 ns; Loc. = M4K_X17_Y4; Fanout = 1; MEM Node = 'ram_da:inst6\|altsyncram:altsyncram_component\|altsyncram_mrg1:auto_generated\|ram_block1a15~porta_datain_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.116 ns" { Yx2 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 503 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.686 ns ( 75.07 % ) " "Info: Total cell delay = 1.686 ns ( 75.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 24.93 % ) " "Info: Total interconnect delay = 0.560 ns ( 24.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.246 ns" { Yx2 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.246 ns" { Yx2 {} Yx2~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.235 ns" { Yx2 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.235 ns" { Yx2 {} Yx2~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.545ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.246 ns" { Yx2 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.246 ns" { Yx2 {} Yx2~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 503 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "db/altsyncram_mrg1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_mrg1.tdf" 503 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 {} } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.235 ns" { Yx2 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.235 ns" { Yx2 {} Yx2~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_memory_reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.545ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.246 ns" { Yx2 ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.246 ns" { Yx2 {} Yx2~out0 {} ram_da:inst6|altsyncram:altsyncram_component|altsyncram_mrg1:auto_generated|ram_block1a15~porta_datain_reg0 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "MEMR memory ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~portb_address_reg0 memory ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\] 255.95 MHz 3.907 ns Internal " "Info: Clock \"MEMR\" has Internal fmax of 255.95 MHz between source memory \"ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~portb_address_reg0\" and destination memory \"ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\]\" (period= 3.907 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.323 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~portb_address_reg0 1 MEM M4K_X17_Y18 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y18; Fanout = 2; MEM Node = 'ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~portb_address_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_5bp1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_5bp1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.323 ns) 3.323 ns ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\] 2 MEM M4K_X17_Y18 2 " "Info: 2: + IC(0.000 ns) + CELL(3.323 ns) = 3.323 ns; Loc. = M4K_X17_Y18; Fanout = 2; MEM Node = 'ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "db/altsyncram_5bp1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_5bp1.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.323 ns ( 100.00 % ) " "Info: Total cell delay = 3.323 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] {} } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns - Smallest " "Info: - Smallest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MEMR destination 6.057 ns + Shortest memory " "Info: + Shortest clock path from clock \"MEMR\" to destination memory is 6.057 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns MEMR 1 CLK PIN_225 5 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_225; Fanout = 5; CLK Node = 'MEMR'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { MEMR } "NODE_NAME" } } { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { 336 -136 32 352 "MEMR" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.088 ns) 2.830 ns log_ctrl_m:inst\|inst4 2 COMB LC_X8_Y10_N2 112 " "Info: 2: + IC(1.607 ns) + CELL(0.088 ns) = 2.830 ns; Loc. = LC_X8_Y10_N2; Fanout = 112; COMB Node = 'log_ctrl_m:inst\|inst4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.695 ns" { MEMR log_ctrl_m:inst|inst4 } "NODE_NAME" } } { "log_ctrl_m.bdf" "" { Schematic "H:/U2/project/RAM/log_ctrl_m.bdf" { { 256 232 296 304 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.686 ns) + CELL(0.541 ns) 6.057 ns ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\] 3 MEM M4K_X17_Y18 2 " "Info: 3: + IC(2.686 ns) + CELL(0.541 ns) = 6.057 ns; Loc. = M4K_X17_Y18; Fanout = 2; MEM Node = 'ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|q_b\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.227 ns" { log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "db/altsyncram_5bp1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_5bp1.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.764 ns ( 29.12 % ) " "Info: Total cell delay = 1.764 ns ( 29.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 70.88 % ) " "Info: Total interconnect delay = 4.293 ns ( 70.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.057 ns" { MEMR log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.057 ns" { MEMR {} MEMR~out0 {} log_ctrl_m:inst|inst4 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] {} } { 0.000ns 0.000ns 1.607ns 2.686ns } { 0.000ns 1.135ns 0.088ns 0.541ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MEMR source 6.069 ns - Longest memory " "Info: - Longest clock path from clock \"MEMR\" to source memory is 6.069 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns MEMR 1 CLK PIN_225 5 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_225; Fanout = 5; CLK Node = 'MEMR'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { MEMR } "NODE_NAME" } } { "pxi_dsp_da.bdf" "" { Schematic "H:/U2/project/RAM/pxi_dsp_da.bdf" { { 336 -136 32 352 "MEMR" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.088 ns) 2.830 ns log_ctrl_m:inst\|inst4 2 COMB LC_X8_Y10_N2 112 " "Info: 2: + IC(1.607 ns) + CELL(0.088 ns) = 2.830 ns; Loc. = LC_X8_Y10_N2; Fanout = 112; COMB Node = 'log_ctrl_m:inst\|inst4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.695 ns" { MEMR log_ctrl_m:inst|inst4 } "NODE_NAME" } } { "log_ctrl_m.bdf" "" { Schematic "H:/U2/project/RAM/log_ctrl_m.bdf" { { 256 232 296 304 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.686 ns) + CELL(0.553 ns) 6.069 ns ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~portb_address_reg0 3 MEM M4K_X17_Y18 2 " "Info: 3: + IC(2.686 ns) + CELL(0.553 ns) = 6.069 ns; Loc. = M4K_X17_Y18; Fanout = 2; MEM Node = 'ram2:inst3\|alt3pram:alt3pram_component\|altdpram:altdpram_component2\|altsyncram:ram_block\|altsyncram_5bp1:auto_generated\|ram_block1a7~portb_address_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.239 ns" { log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_5bp1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_5bp1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 29.26 % ) " "Info: Total cell delay = 1.776 ns ( 29.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 70.74 % ) " "Info: Total interconnect delay = 4.293 ns ( 70.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.069 ns" { MEMR log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.069 ns" { MEMR {} MEMR~out0 {} log_ctrl_m:inst|inst4 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 {} } { 0.000ns 0.000ns 1.607ns 2.686ns } { 0.000ns 1.135ns 0.088ns 0.553ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.057 ns" { MEMR log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.057 ns" { MEMR {} MEMR~out0 {} log_ctrl_m:inst|inst4 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] {} } { 0.000ns 0.000ns 1.607ns 2.686ns } { 0.000ns 1.135ns 0.088ns 0.541ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.069 ns" { MEMR log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.069 ns" { MEMR {} MEMR~out0 {} log_ctrl_m:inst|inst4 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 {} } { 0.000ns 0.000ns 1.607ns 2.686ns } { 0.000ns 1.135ns 0.088ns 0.553ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "db/altsyncram_5bp1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_5bp1.tdf" 256 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "db/altsyncram_5bp1.tdf" "" { Text "H:/U2/project/RAM/db/altsyncram_5bp1.tdf" 34 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] {} } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.057 ns" { MEMR log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.057 ns" { MEMR {} MEMR~out0 {} log_ctrl_m:inst|inst4 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|q_b[7] {} } { 0.000ns 0.000ns 1.607ns 2.686ns } { 0.000ns 1.135ns 0.088ns 0.541ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.069 ns" { MEMR log_ctrl_m:inst|inst4 ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.069 ns" { MEMR {} MEMR~out0 {} log_ctrl_m:inst|inst4 {} ram2:inst3|alt3pram:alt3pram_component|altdpram:altdpram_component2|altsyncram:ram_block|altsyncram_5bp1:auto_generated|ram_block1a7~portb_address_reg0 {} } { 0.000ns 0.000ns 1.607ns 2.686ns } { 0.000ns 1.135ns 0.088ns 0.553ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}