{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 29 22:08:00 2008 " "Info: Processing started: Wed Oct 29 22:08:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder1 -c adder1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder1 -c adder1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adder1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder1-m " "Info: Found design unit 1: adder1-m" {  } { { "adder1.vhd" "" { Text "E:/QuartueII/adder1/adder1.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 adder1 " "Info: Found entity 1: adder1" {  } { { "adder1.vhd" "" { Text "E:/QuartueII/adder1/adder1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "adder1 " "Info: Elaborating entity \"adder1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "7 " "Info: Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Info: Implemented 2 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Allocated 156 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 29 22:08:04 2008 " "Info: Processing ended: Wed Oct 29 22:08:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 29 22:08:06 2008 " "Info: Processing started: Wed Oct 29 22:08:06 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off adder1 -c adder1 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder1 -c adder1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "adder1 EP1C6Q240C6 " "Info: Selected device EP1C6Q240C6 for design \"adder1\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "7 Top " "Info: Previous placement does not exist for 7 of 7 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C6 " "Info: Device EP1C12Q240C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 24 " "Info: Pin ~nCSO~ is reserved at location 24" {  } { { "d:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartusii/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 37 " "Info: Pin ~ASDO~ is reserved at location 37" {  } { { "d:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartusii/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "5 5 " "Warning: No exact pin location assignment(s) for 5 pins of 5 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum " "Info: Pin sum not assigned to an exact location on the device" {  } { { "d:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartusii/quartus/bin/pin_planner.ppl" { sum } } } { "adder1.vhd" "" { Text "E:/QuartueII/adder1/adder1.vhd" 5 -1 0 } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { sum } "NODE_NAME" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { sum } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cout " "Info: Pin cout not assigned to an exact location on the device" {  } { { "d:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartusii/quartus/bin/pin_planner.ppl" { cout } } } { "adder1.vhd" "" { Text "E:/QuartueII/adder1/adder1.vhd" 5 -1 0 } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { cout } "NODE_NAME" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { cout } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "cin " "Info: Pin cin not assigned to an exact location on the device" {  } { { "d:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartusii/quartus/bin/pin_planner.ppl" { cin } } } { "adder1.vhd" "" { Text "E:/QuartueII/adder1/adder1.vhd" 4 -1 0 } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b " "Info: Pin b not assigned to an exact location on the device" {  } { { "d:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartusii/quartus/bin/pin_planner.ppl" { b } } } { "adder1.vhd" "" { Text "E:/QuartueII/adder1/adder1.vhd" 4 -1 0 } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { b } "NODE_NAME" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { b } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a " "Info: Pin a not assigned to an exact location on the device" {  } { { "d:/quartusii/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartusii/quartus/bin/pin_planner.ppl" { a } } } { "adder1.vhd" "" { Text "E:/QuartueII/adder1/adder1.vhd" 4 -1 0 } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { a } "NODE_NAME" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { a } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}