-------------------------------------------------------------------------- Copyright 1997-1998 VAutomation Inc. Nashua NH USA. -- Visit HTTP://www.vautomation.com for mor details on our other-- Synthesizable microprocessor and peripheral cores.---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- This program is distributed in the hope that it will be useful,-- but WITHOUT ANY WARRANTY; without even the implied warranty of-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the-- GNU General Public License for more details.---- The GNU Public License can be found at HTTP://www.gnu.org.-- -- The copyright notice above MUST remain in the source code at all-- times!---- File: vspi.vhd-- Revision: $Name: REV9910 $-- Gate Count: 500 gates (LSI Logic 10K)-- Description:----      Serial Peripheral Interface (SPI)---- The VSPI core implements an SPI interface compatible with the many-- serial EEPROMs, and microcontrollers. The VSPI core is typically used-- as an SPI master, but it can be configured as an SPI slave as well.---- The SPI bus is a 3 wire bus that in effect links a serial shift-- register between the "master" and the "slave". Typically both the-- master and slave have an 8 bit shift register so the combined-- register is 16 bits. When an SPI transfer takes place, the master and-- slave shift their shift registers 8 bits and thus exchange their 8-- bit register values.---- The VPSI core is completely software configurable. The clock-- polarity, clock phase, the clock frequency in master mode, and the-- number of bits to be transferred are all software programmable. These-- configuration bits are usually determined by the capabilities of the-- other device you wish to communicate with.---- SPI supports multiple slaves on a single 3 wire bus by using seperate-- SLaVe SELect signals (SVLSEL) to enable the desired slave. Multiple-- masters are also supported and some support is provided for detecting-- collisions when multiple masters attempt to transfer at the same-- time.---- A Wired-OR mode is provided which allows multiple masters to collide-- on the bus without risk of damage. In this mode, an external pullup-- resisitor is required on the SI and SO pins. WOR mode also allows the-- SPI bus to operate as a 2 wire bus by connecting the SI and SO pins-- together to form a single bidirectional data pin.---- Generally, pullups are recommended on all of the external SPI signals-- to insure they are held in a valid state even when the VSPI core is-- disabled.---- Limitations:--      When operating as a slave, the SPI clock signal (SCK) must be--      slower than 1/8th of the CPU clock. 1/16th is recommended. Note--      that this core is fully synchronous to the cpu CLK and thus SCK--      is sampled and then operated on. This results in 3 to 4 clocks--      of delay which will violate the SPI spec if SCK is faster than--      1/8th of the CPU clock. When the VSPI core is in master mode, it--      operates exactly on the proper edges since it is generating SCK.----      The VSPI core was specifically designed to be an SPI master and--      to be connected to a microprocessor such as VAutomations--      V8-uRISC CPU. This core also has the capability to be a slave--      but that feature is considered secondary which is why it is--      speed limited.---- Register Definition:-- Addr Name    R/W     Description--  0   DOUT    W       8 Bit data out register--  0   DIN     R       8 Bit data in register--  1   CTL     R/W     Control Register--                      [0]=Reserved.--                      [1]=MSTENB      Enable SPI master mode--                      [2]=WOR Wire-OR mode enabled--                      [3]=CKPOL       Clock Polarity 1=SCK idles high,--                                      0=SCK idles low--                      [4]=PHASE       Phase Select--                      [6:5]=DVD       Clock divide - 00=8, 01=16,--                                      10=32, 11=64--                      [7]=IRQENB      Interrupt enable--  2   STATUS  R/W     Interrupt Status register--                      Each bit of the status register is cleared to--                      zero by by writting ONE to the respective bit.--                      [7]=IRQ Interrupt active--                              Set at the end of a master mode--                              transfer, or when SLVSEL goes high on a--                              slave transfer--                      [6]=Overrun--                              This bit is set when the DOUT register--                              is written while an SPI transfer is in--                              progress.--                      [5]=COL--                              This bit is set when there is a master--                              mode collision between multiple SPI--                              masters. It is set when SLVSEL goes low--                              while MSTENB=1.--                      [2:4]=zero--                      [1]=TXRUN--                              1=Master mode operation underway.--                              This bit is read only.--                      [0]=SLVSEL--                              This bit corresponds to the SLVSEL pin--                              on the VSPI core (note that this is--                              normally interted at the IO pin). read--                              only.--  3   SSEL    R/W     Slave Select/bit count register--                      SSEL[7:5]--                              Number of bits to shift in master mode, --                              000=8 bits, 001=1 bit, 111=7 bits.--                      SSEL[4:0]--                              5 individual Slave Selects for master--                              mode---- The VSPI core operates in two fundamentally different modes based on-- the PHASE bit (CTL[4]). The two modes are depicted in the timing-- diagrams below. The key difference centers around the fact that SPI-- data is clocked out on one edge of the clock, and sampled on the-- other. The two modes select where the opposite edge DFF is placed.-- When PHASE=0, a negative edge flop is inserted into the shift_in-- path. The shift_out data is tricky because we must output data from-- the TX_HOLD register for the first bit as we have not seen a clock on-- SCK to clock the data into the shift register. When PHASE=1, the-- negative edge flop is inserted into the shift_out path to hold the-- data for an extra 1/2 clock.---- Microprocessor interface--      The VSPI microprocessor interface is quite simple and connects-- easily to VAutomations V8-uRISC CPU. Transfers are fully synchronous-- to the CLK signal. When CHIP_SEL and WRITE are both active at the-- rising edge of CLK, a write to the desired register occurs. CHIP_SEL-- and WRITE should only be active for 1 clock cycle.---- Timing diagram:---- PHASE=0 (POLCK=0 shown, invert SCKI if POLCK=1)-- Cycle #     | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |--                _   _   _   _   _   _   _   _      -- SCK    _______| |_| |_| |_| |_| |_| |_| |_| |_____--              ___ ___ ___ ___ ___ ___ ___ ___-- MOSI  ------<_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_>-------            _____ ___ ___ ___ ___ ___ ___ _______-- MISO  ----<___7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_XXXX>---            _____________________________________-- SLVSEL ___/                                     \_-- Shift register runs on the second edge of SCKI. A negative edge flop-- is placed in the shift_in path to sample data on the first edge of-- SCKI.-- PHASE=1 (POLCK=0 shown, invert SCKI if POLCK=1)-- Cycle #       | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |--                _   _   _   _   _   _   _   _      -- SCK   ________| |_| |_| |_| |_| |_| |_| |_| |_______--                ___ ___ ___ ___ ___ ___ ___ ___-- MOSI  --------<_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_>-------                _ ___ ___ ___ ___ ___ ___ _________-- MISO  ----XXXXX_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_____>---            _______________________________________-- SLVSEL ___/                                       \_-- Shift register runs on the second edge of SCKI. A negative edge flop-- is placed in the shift_out path to hold data data for an extra 1/2-- clock.---- Crude block diagram:---- DATAIN--------------------------+--                                 |--                    |\           |-- MISO-------+-------> \      +---v--------+                |\--            |       |  >-----> 8bit Shift >-------+--------> \--            |    +--> /      |> Register  |       |        |  >-->MOSI--            |    |  |/       +---v--------+       |   +----> /        --            |    |               |                |   |    |/--            |    |               +---DATAOUT      |   |      --            |    |                                |   |      --            |    +-------------------------+      |   |               --            |     +------------------------|------+   |--            |     |  |\                    |          | --            |     +--> \        +----+     |          | --            |        |  >------->Neg >-----+----------+ --            +--------> /        |DFF |                  --                     |/        O|>   |                  --                                +----+                  -- Not shown are the control and status registers, the master mode bit-- counters and other control logic.-- -- IO cell Requirements:-- The IO cells required for the SPI bus are quite simple. The following-- VHDL code will synthesize to the appropriate cells.----   miso <= misoo when misoe='1' ELSE 'Z';  -- tristate buffer--   mosi <= mosio when mosie='1' ELSE 'Z';  -- tristate buffer--   sck  <= scko  when scke ='1' ELSE 'Z';  -- tristate buffer------------------------------------------------------------------------- This product is licensed to:-- $name$ of $company$-- for use at site(s):-- $site$--------------Revision History------------------------------------------- $Log: vspi.vhd,v $-- Revision 1.7  1999/09/09 16:02:37  scott-- std_ulogic'ified, numeric_std'ified, RMM'ified---- Revision 1.6  1999/02/17 00:51:50  eric-- Added more checking on various error conditions.---- Revision 1.5  1999/02/02 19:56:13  eric-- Changes to fully sync to the CPU clock.---- Revision 1.4  1998/10/16 13:54:57  eric-- Corrected missing sensitiviy list signals for FIRST_BIT.---- Revision 1.3  1998/09/30 14:56:56  eric-- Initial release level.---- Revision 1.2  1998/09/24 02:51:44  eric-- Master mode works in phase=0.-------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all; -- we use IEEE standard 1164 logic types.use ieee.numeric_std.all;    -- + and - operatorsentity vspi is  ----------------------------ENTITY---------------------  port(    clk      : in  std_ulogic;   -- everything clocks on rising edge    rst      : in  std_ulogic;   -- reset    addr     : in  std_ulogic_vector(1 downto 0);  -- address bus    datain   : in  std_ulogic_vector(7 downto 0);  -- data bus    dataout  : out std_ulogic_vector(7 downto 0);  -- data bus    write    : in  std_ulogic;   -- write enable    chip_sel : in  std_ulogic;   -- device Select    irq      : out std_ulogic;   -- interrupt request    -- SPI interface without IO cells    misoe    : out std_ulogic;   -- MISO tristate enable    misoi    : in  std_ulogic;   -- Master in/Slave out data in    misoo    : out std_ulogic;   -- MISO data out    mosie    : out std_ulogic;   -- MOSI tristate enable    mosii    : in  std_ulogic;   -- Master out/Slave in data in    mosio    : out std_ulogic;   -- MOSI data out    scke     : out std_ulogic;   -- SCK Clock tristate enable    scki     : in  std_ulogic;    -- SCK Clock input (shift register runs on this)    scko     : out std_ulogic;   -- SCK clock output    slvsele  : out std_ulogic;   -- tristate enable for slave selects    slvselo  : out std_ulogic_vector(4 downto 0);    -- external slave selects    slvsel   : in  std_ulogic    -- Slave Select    );end vspi;architecture empty of vspi is -------- ARCHITECTURE empty --------  -- This architecture is provided to easily and quickly remove the SPI  -- core for your ASIC or FPGA.begin   dataout <= (others => '0');  irq     <= '0';  misoo   <= '0';  misoe   <= '0';  mosie   <= '0';  mosio   <= '0';  scko    <= '0';  scke    <= '0';  slvsele <= '0';  slvselo <= "00000";end empty;architecture rtl of vspi is -----------ARCHITECTURE rtl-----------  attribute sync_set_reset : string; -- required for synopsys  attribute sync_set_reset of rst : signal is "true";  -- required for synopsys  signal bit_ctr     : std_ulogic_vector(2 downto 0);  -- # bits in a byte  signal ctl_reg     : std_ulogic_vector(7 downto 0);  -- control register  signal col_flag    : std_ulogic; -- collision flag  signal dvd_ctr     : std_ulogic_vector(4 downto 0); -- clock divider  signal dvd2        : std_ulogic;  signal dvd_zero    : std_ulogic; -- clk divider controls  signal irq_flag    : std_ulogic;  -- local version of IRQ before gated with IRQENB  signal master_mode : std_ulogic; -- Master mode when 1  signal misoe_lcl   : std_ulogic; -- local version