Info: Detected gated clock "ballctrl:ucpu|comb~0" as buffer
Info: Clock "clk" Internal fmax is restricted to 200.0 MHz between source register "ball:uball|lamp[3]" and destination register "ball:uball|lamp[2]"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_B24; Fanout = 3; REG Node = 'ball:uball|lamp[3]'
            Info: 2: + IC(0.900 ns) + CELL(1.000 ns) = 1.900 ns; Loc. = LC2_B23; Fanout = 3; REG Node = 'ball:uball|lamp[2]'
            Info: Total cell delay = 1.000 ns ( 52.63 % )
            Info: Total interconnect delay = 0.900 ns ( 47.37 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.400 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 11; CLK Node = 'clk'
                Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_B23; Fanout = 3; REG Node = 'ball:uball|lamp[2]'
                Info: Total cell delay = 2.000 ns ( 83.33 % )
                Info: Total interconnect delay = 0.400 ns ( 16.67 % )
            Info: - Longest clock path from clock "clk" to source register is 2.400 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 11; CLK Node = 'clk'
                Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_B24; Fanout = 3; REG Node = 'ball:uball|lamp[3]'
                Info: Total cell delay = 2.000 ns ( 83.33 % )
                Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: + Micro clock to output delay of source is 0.500 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: Clock "bain" has Internal fmax of 63.29 MHz between source register "ballctrl:ucpu|serve" and destination register "board:ubda|couclk" (period= 15.8 ns)
    Info: + Longest register to register delay is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu|serve'
        Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC6_B22; Fanout = 1; COMB Node = 'board:ubda|couclk~1'
        Info: 3: + IC(0.300 ns) + CELL(1.000 ns) = 3.000 ns; Loc. = LC2_B22; Fanout = 9; REG Node = 'board:ubda|couclk'
        Info: Total cell delay = 2.400 ns ( 80.00 % )
        Info: Total interconnect delay = 0.600 ns ( 20.00 % )
    Info: - Smallest clock skew is -4.300 ns
        Info: + Shortest clock path from clock "bain" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 6; CLK Node = 'bain'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_B22; Fanout = 9; REG Node = 'board:ubda|couclk'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "bain" to source register is 6.700 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 6; CLK Node = 'bain'
            Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 3.900 ns; Loc. = LC3_B18; Fanout = 1; COMB Node = 'ballctrl:ucpu|bdout'
            Info: 3: + IC(1.200 ns) + CELL(1.600 ns) = 6.700 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu|serve'
            Info: Total cell delay = 5.200 ns ( 77.61 % )
            Info: Total interconnect delay = 1.500 ns ( 22.39 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Micro setup delay of destination is 0.600 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "bbin" has Internal fmax of 64.94 MHz between source register "ballctrl:ucpu|serve" and destination register "board:ubdb|couclk" (period= 15.4 ns)
    Info: + Longest register to register delay is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu|serve'
        Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC7_B22; Fanout = 1; COMB Node = 'board:ubdb|couclk~1'
        Info: 3: + IC(0.300 ns) + CELL(1.000 ns) = 3.000 ns; Loc. = LC4_B22; Fanout = 9; REG Node = 'board:ubdb|couclk'
        Info: Total cell delay = 2.400 ns ( 80.00 % )
        Info: Total interconnect delay = 0.600 ns ( 20.00 % )
    Info: - Smallest clock skew is -4.100 ns
        Info: + Shortest clock path from clock "bbin" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 6; CLK Node = 'bbin'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_B22; Fanout = 9; REG Node = 'board:ubdb|couclk'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "bbin" to source register is 6.500 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 6; CLK Node = 'bbin'
            Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 3.700 ns; Loc. = LC3_B18; Fanout = 1; COMB Node = 'ballctrl:ucpu|bdout'
            Info: 3: + IC(1.200 ns) + CELL(1.600 ns) = 6.500 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu|serve'
            Info: Total cell delay = 5.000 ns ( 76.92 % )
            Info: Total interconnect delay = 1.500 ns ( 23.08 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Micro setup delay of destination is 0.600 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "bain" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "board:ubda|serclk" and destination pin or register "ballctrl:ucpu|serve" for clock "bain" (Hold time is 100 ps)
    Info: + Largest clock skew is 4.300 ns
        Info: + Longest clock path from clock "bain" to destination register is 6.700 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 6; CLK Node = 'bain'
            Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 3.900 ns; Loc. = LC3_B18; Fanout = 1; COMB Node = 'ballctrl:ucpu|bdout'
            Info: 3: + IC(1.200 ns) + CELL(1.600 ns) = 6.700 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu|serve'
            Info: Total cell delay = 5.200 ns ( 77.61 % )
            Info: Total interconnect delay = 1.500 ns ( 22.39 % )
        Info: - Shortest clock path from clock "bain" to source register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 6; CLK Node = 'bain'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_B22; Fanout = 3; REG Node = 'board:ubda|serclk'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: - Micro clock to output delay of source is 0.500 ns
    Info: - Shortest register to register delay is 3.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B22; Fanout = 3; REG Node = 'board:ubda|serclk'
        Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC1_B22; Fanout = 2; COMB Node = 'ballctrl:ucpu|serclk'
        Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 3.700 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu|serve'
        Info: Total cell delay = 3.100 ns ( 83.78 % )
        Info: Total interconnect delay =