module FIFO(datain,we,re,reset,clk,full,empty,dataout);
   input datain;  //receive wanr dataout
   input we;  //write enable,active high
   input re;  //read enable,active high
   input reset;  //globle reset signal
   input clk;  //system CLK8M
   output full;  //symbol of fifo full,active high
   output empty;  //symbol of fifo empty,active high
   output dataout;  //fifo data output
parameter depth=8; //fifo RAM depth,can be changed from TOP or BRG module

reg [depth-1:0] RAM;
reg wp,rp,in_full,full,empty,dataout;

always //fifo write address description
 begin: RAM_Block
   @(posedge clk)
  if (we==1 && in_full==0) 
 RAM[wp]=datain;
 end

always
 begin: Wp_Block //write point description
   if (reset==1)        
wp<=0;
@(posedge clk)
if (we==1 && in_full==0)
  if (wp==depth-1)
    wp<=0;
     else 
    wp<=wp+1;
 end

always
 begin: Rp_Block //read point description
if (reset==1)
  rp<=depth-1;
@(negedge clk)
if (re==1 && empty==0  )  
if (rp==depth-1)
 rp<=0;
     else
 rp<=rp+1;
 end

always
 begin: Empty_Block //fifo empty description
   if (reset==1)
  empty<=1;
else @ (negedge clk)
if ((rp==wp-2 || (rp==depth-1 && wp==1) || (rp==depth-2 && wp==0)) && re==1 && we==0)
  empty<=1;
   else if (empty==1 && we==1)
  empty<=0;
 end

always
 begin: IN_full_Block //fifo full description 
   if (reset==1)
  in_full<=0;
else @ (posedge clk)
if (rp==wp && we==1 && re==0)
  in_full<=1;
else if (in_full==1 && re==0)
  in_full<=0;
 end 

always
 begin
   full<=in_full;
   dataout<=RAM[rp];//fifo read address description
 end

endmodule