library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.commonConstants.all;

entity ram is port (
        reset, en, r_w: in STD_LOGIC;
        aBus: in STD_LOGIC_VECTOR(adrLength-1 downto 0);
        dBus: inout STD_LOGIC_VECTOR(wordSize-1 downto 0));
end ram;

architecture ramArch of ram is
constant resAdrLength: integer := 6; -- address length restricted within architecture
constant memSize: integer := 2**resAdrLength;
type ram_typ is array(0 to memSize-1) of STD_LOGIC_VECTOR(wordSize-1 downto 0);
signal ram: ram_typ;
begin
	process(reset, en, r_w, aBus, dBus) begin
	  	if reset = '1' then
				-- sum.bin : load 0, add
				ram(0) <= x""; -- load 0
		      	-- basic instruction check
--	        	ram(0)  <= x"1a0f"; -- immediate load
--				ram(1)  <= x"2010"; -- direct load
--		        ram(2)  <= x"3030"; -- indirect load
--		        ram(3)  <= x"4034"; -- direct store
--		        ram(4)  <= x"0001"; -- negate
--		        ram(5)  <= x"2034"; -- direct load
--		        ram(6)  <= x"0001"; -- negate
--		        ram(7)  <= x"5032"; -- indirect store
--		        ram(8)  <= x"0001"; -- negate
--		        ram(9)  <= x"1fff"; -- immediate load
--		        ram(10) <= x"a008"; -- add
--		        ram(11) <= x"700d"; -- brZero
--		        ram(12) <= x"0000"; -- halt
--		        ram(13) <= x"1400"; -- immediate load
--		        ram(14) <= x"8010"; -- brPos
--		        ram(15) <= x"0000"; -- halt
--		        ram(16) <= x"0001"; -- negate
--		        ram(17) <= x"9013"; -- brNeg
--		        ram(18) <= x"0000"; -- halt
--		        ram(19) <= x"6015"; -- branch
--		        ram(20) <= x"0000"; -- halt
--		        ram(21) <= x"8014"; -- brPos
--		        ram(22) <= x"7014"; -- brZero
--		        ram(23) <= x"0001"; -- negate
--		        ram(24) <= x"9014"; -- brNeg
--		        ram(25) <= x"0000"; -- halt
--		        ram(48) <= x"0031"; -- pointer for iload
--		        ram(49) <= x"5af0"; -- target of iload
--		        ram(50) <= x"0033"; -- pointer for istore
--		        ram(51) <= x"0000"; -- target of istore
--		        ram(52) <= x"f5af"; -- target of dstore
		elsif en = '1' and r_w = '0' then
	  		ram(conv_integer(unsigned(aBus(resAdrLength-1 downto 0)))) <= dBus;
		end if;
	end process;
	dBus <= ram(conv_integer(unsigned(aBus(resAdrLength-1 downto 0))))
  			when reset = '0' and en = '1' and r_w = '1' else
			(dbus'range => 'Z');
end ramArch;