library verilog;use verilog.vl_types.all;entity ADDSUB is    port(        add_sub         : in     vl_logic;        dataa           : in     vl_logic_vector(15 downto 0);        datab           : in     vl_logic_vector(15 downto 0);        result          : out    vl_logic_vector(15 downto 0)    );end ADDSUB;