library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt10bcd is
    Port (	clkin	:in std_logic;
			co		:out std_logic;
    		qout	:out std_logic_vector(3 downto 0)
			);
end cnt10bcd;

architecture behavioral of cnt10bcd is
signal	cnt10	:std_logic_vector(3 downto 0);
begin
	process(clkin)
	begin
		if clkin'event and clkin='1' then
			if	cnt10="1001"	then
				cnt10<="0000";
				co<='1';
			else
				cnt10<=cnt10 + 1;
				co<='0';
			end if;
		end if;
	end process;
	qout<=cnt10;

end behavioral;