library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity keydetc is
    Port (	clk_5ms	:in std_logic;
--			clk_1us	:in std_logic;
    		adj,up	:in std_logic;
			mode	:out std_logic_vector(3 downto 0);
			inc	:out std_logic
		);
end keydetc;

architecture behavioral of keydetc is
signal	clkmode	:std_logic_vector(3 downto 0):="1000";
					--clock mode:
					--0001	normal
					--0010	adj. sec.
					--0100	adj. min.
					--1000	adj. hour
signal	adjdly1,adjdly2	:std_logic;
signal	updly1,updly2	:std_logic;
signal	adjkey,inckey	:std_logic;
signal	tm_20ms	:std_logic_vector(2 downto 0):="000";

begin
	process(clk_5ms)
	begin
		if clk_5ms'event and clk_5ms='1' then
			if tm_20ms="100" then	tm_20ms<="000";
			else	tm_20ms<=tm_20ms+1;
		   	end if;
		end if;
	end process;

	process(tm_20ms(2))
	begin
		if tm_20ms(2)'event and tm_20ms(2)='1' then
			adjdly1<=adj;
			adjdly2<=adjdly1;
			updly1<=up;
			updly2<=updly1;
		end if;
	end process;
	adjkey<=not adjdly1 and adjdly2;
	inckey<=not updly1 and updly2;
	process(adjkey)
	begin
		if adjkey'event and adjkey='1' then
			if clkmode="0001" then	clkmode<="0010";
				elsif clkmode="0010" then	clkmode<="0100";
				elsif clkmode="0010" then	clkmode<="0001";
				elsif clkmode="0100" then	clkmode<="1000";
				else  clkmode<="0001";
			 end if;
		end if;
	end process;
	mode<=clkmode;
	inc<=inckey;

end behavioral;