library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt24bcd is
    Port (	clkin	:in std_logic;
    		qout	:out std_logic_vector(5 downto 0)
			);
end cnt24bcd;

architecture behavioral of cnt24bcd is
signal	cnt	:std_logic_vector(5 downto 0);
signal	tmp1	:std_logic;

begin
	process(clkin)
	begin
	if clkin='1' and clkin'event then
		if cnt(3 downto 0)="1001" or cnt="100011" then
			cnt(3 downto 0)<="0000";
			tmp1<='1';
		else
			cnt(3 downto 0)<=cnt(3 downto 0) + 1;
			tmp1<='0';
		end if;
	end if;
	end process;

	process(tmp1)
	begin
		if tmp1='1' and tmp1'event then
			if cnt="100011" then
				cnt(5 downto 4)<="00";
			else
				cnt(5 downto 4)<=cnt(5 downto 4) + 1;
			end if;
		end if;
	end process;
	qout<=cnt;

end behavioral;