library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hou is
port (clk, m, ena: in std_logic;
             cout: out std_logic;
           dh, qh: buffer std_logic_vector(3 downto 0);
     dh_24, qh_24: buffer std_logic_vector(3 downto 0);
               af: buffer std_logic_vector(1 downto 0));
end hou;
architecture one of hou is
    signal dhf, qhf, dht, qht: std_logic_vector(3 downto 0);
    signal tf: std_logic_vector(1 downto 0);
    signal s: integer range 0 to 1;
begin
 hour_24:process (clk,ena)
   begin
   if ena='1' then
    if rising_edge(clk) then
       if (qhf="0010" and dhf="0011") then cout <= '1';
       else cout<= '0';
       end if;
       if qhf="0010" and dhf="0011" then qhf<="0000"; dhf<="0000";               
       elsif dhf<"1001" then dhf<=dhf+1;
          elsif dhf="1001" then qhf<=qhf+1; dhf<="0000";
       end if;
    end if;     
   end if;
end process hour_24;
 hour_12:process (clk, tf, ena)
   begin
   if ena='1' then
    if rising_edge(clk) then
      case s is
        when 0=>
       if (qht="0001" and dht="0010") then qht<="0000"; dht<="0001";tf<="01";s<=1;             
       elsif dht<"1001" then dht<=dht+1;
       elsif dht="1001" then qht<=qht+1; dht<="0000";
       end if;
        when 1=>
       if (qht="0001" and dht="0010") then qht<="0000"; dht<="0001";tf<="10";s<=0;      
       elsif dht<"1001" then dht<=dht+1;
       elsif dht="1001" then qht<=qht+1; dht<="0000";
       end if;
        when others=>
       null;
       end case;
    end if;
   end if;
end process hour_12;
 m_hour:process(clk,m,dhf,qhf,dht,qht,tf)
   begin
    dh_24<=dhf;
    qh_24<=qhf;
    if m='0' then qh<=qhf;dh<=dhf;af<="00";
    else qh<=qht;dh<=dht;af<=tf;
    end if;
end process m_hour;
end one;