library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity houclock is
port (clk1khz, ena, clkadd: in std_logic;
      dth, qth: in std_logic_vector(3 downto 0);
      tf: out std_logic;
      dh, qh: out std_logic_vector(3 downto 0));
end houclock;
architecture one of houclock is
    signal dhf, qhf: std_logic_vector(3 downto 0);
begin
 process (clk1khz,ena,clkadd,dth,qth,dhf,qhf)
   begin
   if ena='0' then
    if rising_edge(clkadd) then
     if qhf="0010" and dhf="0011" then qhf<="0000"; dhf<="0000";               
     elsif dhf<"1001" then dhf<=dhf+1;
        elsif dhf="1001" then qhf<=qhf+1; dhf<="0000";
     end if;
    end if;
   elsif rising_edge(clk1khz) then
       if dth=dhf and qth=qhf then
       tf<='1';
       else tf<='0';
       end if;
   end if;
 dh<=dhf;
 qh<=qhf;
 end process;
end one;