library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift is
port(
clk:in std_logic;
do:out std_logic_vector(1 downto 0)
);
end shift;
architecture a of shift is
signal clkout1:std_logic_vector(9 downto 0);
signal a:std_logic_vector(1 downto 0);
begin
process(clk)
begin
if (clk'event and clk='1') then
if clkout1="1111111111" then
clkout1<="0000000000";
a<= a+1;
else
clkout1<=clkout1+1;
end if;
end if;
end process;
do<= a;
end a;