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<!@TC:1216018004>
#Build: Synplify Pro 8.6.2, Build 013R, Jun 5 2006
#install: D:\Program Files\Synplicity\fpga_862
#OS: Windows XP 5.1
#Hostname: A6FF1236EE004A2
#Mon Jul 14 14:46:42 2008
<a name=compilerReport44>$ Start of Compile
#Mon Jul 14 14:46:42 2008
Synplicity VHDL Compiler, version 3.6t, Build 206R, built Aug 8 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="d:\program files\synplicity\fpga_862\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1216018004> | Setting time resolution to ns
@N: : <a href="e:\my synplyfy\lift\flift.vhd:6:7:6:12:@N::@XP_MSG">flift.vhd(6)</a><!@TM:1216018004> | Top entity is set to FLIFT.
VHDL syntax check successful!
Compiler output is up to date. No re-compile necessary
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="e:\my synplyfy\lift\flift.vhd:6:7:6:12:@N:CD630:@XP_MSG">flift.vhd(6)</a><!@TM:1216018004> | Synthesizing work.flift.behav
@N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="e:\my synplyfy\lift\flift.vhd:18:16:18:18:@N:CD231:@XP_MSG">flift.vhd(18)</a><!@TM:1216018004> | Using onehot encoding for type state_type (stopon1="1000000000")
<font color=#A52A2A>@W:<a href="@W:CG296:@XP_HELP">CG296</a> : <a href="e:\my synplyfy\lift\flift.vhd:26:0:26:7:@W:CG296:@XP_MSG">flift.vhd(26)</a><!@TM:1216018004> | Incomplete sensitivity list - assuming completeness</font>
<font color=#A52A2A>@W:<a href="@W:CG290:@XP_HELP">CG290</a> : <a href="e:\my synplyfy\lift\flift.vhd:28:4:28:7:@W:CG290:@XP_MSG">flift.vhd(28)</a><!@TM:1216018004> | Referenced variable rst is not in sensitivity list</font>
<font color=#A52A2A>@W:<a href="@W:CD604:@XP_HELP">CD604</a> : <a href="e:\my synplyfy\lift\flift.vhd:138:2:138:15:@W:CD604:@XP_MSG">flift.vhd(138)</a><!@TM:1216018004> | OTHERS clause is not synthesized </font>
Post processing for work.flift.behav
<font color=#A52A2A>@W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="e:\my synplyfy\lift\flift.vhd:40:1:40:3:@W:CL112:@XP_MSG">flift.vhd(40)</a><!@TM:1216018004> | Feedback mux created for signal UDSIG. Did you forget the set/reset assignment for this signal?</font>
<font color=#A52A2A>@W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="e:\my synplyfy\lift\flift.vhd:40:1:40:3:@W:CL112:@XP_MSG">flift.vhd(40)</a><!@TM:1216018004> | Feedback mux created for signal pos[2:0]. Did you forget the set/reset assignment for this signal?</font>
<font color=#A52A2A>@W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="e:\my synplyfy\lift\flift.vhd:40:1:40:3:@W:CL112:@XP_MSG">flift.vhd(40)</a><!@TM:1216018004> | Feedback mux created for signal POSITION[2:0]. Did you forget the set/reset assignment for this signal?</font>
<font color=#A52A2A>@W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="e:\my synplyfy\lift\flift.vhd:40:1:40:3:@W:CL112:@XP_MSG">flift.vhd(40)</a><!@TM:1216018004> | Feedback mux created for signal DOORLIGHT. Did you forget the set/reset assignment for this signal?</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="e:\my synplyfy\lift\flift.vhd:145:1:145:3:@W:CL190:@XP_MSG">flift.vhd(145)</a><!@TM:1216018004> | Optimizing register bit DOWNLIGHT(1) to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="e:\my synplyfy\lift\flift.vhd:145:1:145:3:@W:CL190:@XP_MSG">flift.vhd(145)</a><!@TM:1216018004> | Optimizing register bit UPLIGHT(4) to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\my synplyfy\lift\flift.vhd:145:1:145:3:@W:CL169:@XP_MSG">flift.vhd(145)</a><!@TM:1216018004> | Pruning Register DOWNLIGHT(1) </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="e:\my synplyfy\lift\flift.vhd:145:1:145:3:@W:CL169:@XP_MSG">flift.vhd(145)</a><!@TM:1216018004> | Pruning Register UPLIGHT(4) </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="e:\my synplyfy\lift\flift.vhd:40:1:40:3:@N:CL201:@XP_MSG">flift.vhd(40)</a><!@TM:1216018004> | Trying to extract state machine for register STATE
Extracted state machine for register STATE
State machine has 10 reachable states with original encodings of:
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Jul 14 14:46:42 2008
###########################################################]
###########################################################[
<a name=mapperReport45>Synplicity Altera Technology Mapper, Version 8.6.2, Build 027R, Built Aug 11 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
Version 8.6.2
Reading constraint file: E:\My Synplyfy\lift\lift.sdc
Adding property syn_reference_clock1, value "CLK,r=0.0,f=5.0,u=0.0,p=10.0,clockgroup=default_clkgroup_0,rd=0.0,fd=0.0,v=1" to view:work.FLIFT(behav)
Adding property syn_input_delay1, value "r=0.0,f=0.0,rs=0.0,fs=0.0,improve=0,route=2.00,ref=*" to view:work.FLIFT(behav)
Adding property syn_output_delay2, value "r=0.0,f=0.0,rs=0.0,fs=0.0,improve=0,route=2.00,ref=*" to view:work.FLIFT(behav)
Reading constraint file: E:\My Synplyfy\lift\rev_2\flift_fsm.sdc
@N: : <!@TM:1216018004> | Using encoding styles selected by FSM Explorer.
Data created on Wed Jul 09 18:53:21 2008
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1216018004> | Running in 32-bit mode.
@N:<a href="@N:MF258:@XP_HELP">MF258</a> : <!@TM:1216018004> | Gated clock conversion disabled
Adding property syn_encoding in cell FLIFT, value "gray", to instance STATE[0:9]
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="e:\my synplyfy\lift\flift.vhd:40:1:40:3:@W:BN132:@XP_MSG">flift.vhd(40)</a><!@TM:1216018004> | Removing sequential instance CLEARDN, because it is equivalent to instance CLEARUP</font>
@N:<a href="@N:MT204:@XP_HELP">MT204</a> : <!@TM:1216018004> | Because following clock(s) are defined in SDC file, Autoconstrain mode is TURNED OFF
@N:<a href="@N:FA211:@XP_HELP">FA211</a> : <!@TM:1216018004> | CLK
RTL optimization done.
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 21MB peak: 22MB)
Encoding state machine work.FLIFT(behav)-STATE[0:9]
original code -> new code
0000000001 -> 0000
0000000010 -> 0001
0000000100 -> 0011
0000001000 -> 0010
0000010000 -> 0110
0000100000 -> 0111
0001000000 -> 0101
0010000000 -> 0100
0100000000 -> 1100
1000000000 -> 1101
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 49MB)
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 49MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 49MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)
Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 48MB peak: 49MB)
Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 53MB peak: 54MB)
@N:<a href="@N:MF197:@XP_HELP">MF197</a> : <!@TM:1216018008> | Retiming summary : 0 registers retimed to 0
##### BEGIN RETIMING REPORT #####
Retiming summary : 0 registers retimed to 0
Original and Pipelined registers replaced by retiming :
None
New registers created by retiming :
None
##### END RETIMING REPORT #####
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 53MB peak: 54MB)
Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 53MB peak: 54MB)
@N:<a href="@N:BN191:@XP_HELP">BN191</a> : <!@TM:1216018008> | Writing property annotation file E:\My Synplyfy\lift\rev_2\flift.tap.
Writing Analyst data base E:\My Synplyfy\lift\rev_2\flift.srm
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1216018008> | Writing default property annotation file E:\My Synplyfy\lift\rev_2\flift.map.
Writing Verilog Netlist and constraint files
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to E:\My Synplyfy\lift\rev_2\flift.xrf
Found clock FLIFT|CLK with period 1000.00ns
Found clock FLIFT|Q_derived_clock[3] with period 1000.00ns
Found clock FLIFT|Q_derived_clock[0] with period 1000.00ns
All Input Ports in the design have input constraint of 2.00ns
All Output Ports in the design have output constraint of 2.00ns
<a name=timingReport46>##### START OF TIMING REPORT #####[
# Timing Report written on Mon Jul 14 14:46:47 2008
#
Top view: FLIFT
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): E:\My Synplyfy\lift\lift.sdc
E:\My Synplyfy\lift\rev_2\flift_fsm.sdc
@N:<a href="@N:MT195:@XP_HELP">MT195</a> : <!@TM:1216018008> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N:<a href="@N:MT197:@XP_HELP">MT197</a> : <!@TM:1216018008> | Clock constraints cover only FF-to-FF paths associated with the clock..
<a name=performanceSummary47>Performance Summary
*******************
Worst slack in design: 994.387
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------------------------------------
CLK 100.0 MHz NA 10.000 NA NA virtual default_clkgroup_0
FLIFT|CLK 1.0 MHz 178.2 MHz 1000.000 5.613 998.915 inferred Autoconstr_clkgroup_0
FLIFT|Q_derived_clock[0] 1.0 MHz 178.2 MHz 1000.000 5.613 994.387 derived (from FLIFT|CLK) Autoconstr_clkgroup_0
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