?? mc8051_top_srr.htm
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<!@TC:1176175076>
#Build: Synplify Pro 8.6.2, Build 013R, Jun 5 2006
#install: d:\Synplicity\fpga_862
#OS: Windows XP 5.1
#Hostname: LENOVO-41E016C8
#Tue Apr 10 11:17:55 2007
<a name=compilerReport1>$ Start of Compile
#Tue Apr 10 11:17:55 2007
<a name=compilerReport2>Synplicity HDL Compiler, version 3.6t, Build 206R, built Aug 8 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="d:\synplicity\fpga_862\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1176175082> | Setting time resolution to ns
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_p.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_ovcy_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_cy_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_ovcy_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_cy_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\dcml_adjust_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\control_mem_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\control_fsm_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\comb_mltplr_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\comb_divider_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\alumux_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\alucore_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_core_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\dcml_adjust_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\control_mem_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\control_fsm_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\comb_mltplr_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\comb_divider_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\alumux_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\alucore_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_core_struc.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_tmrctr_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_siu_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_control_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_alu_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_tmrctr_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_siu_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_control_struc.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_alu_struc.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_core_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_clockdiv.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_core_struc.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd"
VHDL syntax check successful!
# Tue Apr 10 11:17:57 2007
###########################################################]
@I::"d:\Synplicity\fpga_862\lib\xilinx\unisim.v"
@I::"d:\Synplicity\fpga_862\bin\..\lib\xilinx\unisim.v"
@I::"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_rom.v"
@N:<a href="@N:CG334:@XP_HELP">CG334</a> : <a href="e:\vtest\xilinx\vhdl8051\mc8051\mc8051_rom.v:50:12:50:25:@N:CG334:@XP_MSG">mc8051_rom.v(50)</a><!@TM:1176175082> | Read directive translate_off
@N:<a href="@N:CG333:@XP_HELP">CG333</a> : <a href="e:\vtest\xilinx\vhdl8051\mc8051\mc8051_rom.v:97:12:97:24:@N:CG333:@XP_MSG">mc8051_rom.v(97)</a><!@TM:1176175082> | Read directive translate_on
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="e:\vtest\xilinx\vhdl8051\mc8051\mc8051_rom.v:100:12:100:21:@W:CS141:@XP_MSG">mc8051_rom.v(100)</a><!@TM:1176175082> | Unrecognized synthesis directive attribute</font>
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="e:\vtest\xilinx\vhdl8051\mc8051\mc8051_rom.v:101:13:101:22:@W:CS141:@XP_MSG">mc8051_rom.v(101)</a><!@TM:1176175082> | Unrecognized synthesis directive attribute</font>
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="e:\vtest\xilinx\vhdl8051\mc8051\mc8051_rom.v:105:13:105:22:@W:CS141:@XP_MSG">mc8051_rom.v(105)</a><!@TM:1176175082> | Unrecognized synthesis directive attribute</font>
@I::"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_ram.v"
@N:<a href="@N:CG334:@XP_HELP">CG334</a> : <a href="e:\vtest\xilinx\vhdl8051\mc8051\mc8051_ram.v:56:12:56:25:@N:CG334:@XP_MSG">mc8051_ram.v(56)</a><!@TM:1176175082> | Read directive translate_off
@N:<a href="@N:CG333:@XP_HELP">CG333</a> : <a href="e:\vtest\xilinx\vhdl8051\mc8051\mc8051_ram.v:103:12:103:24:@N:CG333:@XP_MSG">mc8051_ram.v(103)</a><!@TM:1176175082> | Read directive translate_on
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="e:\vtest\xilinx\vhdl8051\mc8051\mc8051_ram.v:106:12:106:21:@W:CS141:@XP_MSG">mc8051_ram.v(106)</a><!@TM:1176175082> | Unrecognized synthesis directive attribute</font>
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="e:\vtest\xilinx\vhdl8051\mc8051\mc8051_ram.v:107:13:107:22:@W:CS141:@XP_MSG">mc8051_ram.v(107)</a><!@TM:1176175082> | Unrecognized synthesis directive attribute</font>
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="e:\vtest\xilinx\vhdl8051\mc8051\mc8051_ram.v:111:13:111:22:@W:CS141:@XP_MSG">mc8051_ram.v(111)</a><!@TM:1176175082> | Unrecognized synthesis directive attribute</font>
Verilog syntax check successful!
# Tue Apr 10 11:17:58 2007
###########################################################]
Duplicate Module/Entity Name AND2, appending...
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