library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity switch is
    Port ( vgadd : in std_logic_vector(14 downto 0);
           convadd : in std_logic_vector(14 downto 0);
           address2 : out std_logic_vector(14 downto 0);
           Q_9 : in std_logic);
end switch;

architecture Behavioral of switch is

begin
process(Q_9)
begin
if(Q_9='1')then
	address2 <= convadd;
else
	address2 <= vgadd;
end if;
end process;


end Behavioral;