?? decoding.vhd
字號:
-- decoding
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity decoding is
port(sel:in std_logic_vector(1 downto 0);
c:in std_logic;
dec3,dec2,dec1,dec0:out std_logic);
end decoding;
architecture rtl of decoding is
begin
process(sel)
begin
if(c='0') then
dec3<='1';dec2<='1';dec1<='1';dec0<='0';
else
if(sel="00") then
dec3<='1';dec2<='1';dec1<='1';dec0<='0';
elsif(sel="01") then
dec3<='1';dec2<='1';dec1<='0';dec0<='1';
elsif(sel="10") then
dec3<='1';dec2<='0';dec1<='1';dec0<='1';
elsif(sel="11") then
dec3<='0';dec2<='1';dec1<='1';dec0<='1';
end if;
end if;
end process;
end rtl;
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