-- 庫(kù)聲明library IEEE;use IEEE.STD_LOGIC_1164.all;use ieee.std_logic_arith.all;-- 實(shí)體聲明entity counter is	generic (	MAX_COUNT : integer := 10 );	port (	clk : in std_logic;	reset_n : in std_logic;	ce : in std_logic;	overflow : out std_logic;		dout : out std_logic_vector(3 downto 0)	);end counter;--}} End of automatically maintained section-- 結(jié)構(gòu)體architecture counter of counter issignal count : integer;begin	dout <= conv_std_logic_vector(count, 4);	-- enter your statements here --	-- 主