?? cpu.vhd
字號(hào):
------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date: 16:22:16 01/04/2008 -- Design Name: -- Module Name: CPU - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity CPU is
port(
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
recv: in std_logic;
send_over: in std_logic;
send: out std_logic;
wr_en: out std_logic;
rd_en: out std_logic;
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(7 downto 0);
addr: out std_logic_vector(7 downto 0)
);end CPU;architecture Behavioral of CPU isbeginend Behavioral;
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