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?? uart_regs.fit.eqn

?? 串行通訊ip核
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S1_q_b[0]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[0]_PORT_B_address_reg = DFFE(S1_q_b[0]_PORT_B_address, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_PORT_A_write_enable = K2L9;
S1_q_b[0]_PORT_A_write_enable_reg = DFFE(S1_q_b[0]_PORT_A_write_enable, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_read_enable = VCC;
S1_q_b[0]_PORT_B_read_enable_reg = DFFE(S1_q_b[0]_PORT_B_read_enable, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_clock_0 = GLOBAL(clk);
S1_q_b[0]_clock_1 = GLOBAL(clk);
S1_q_b[0]_clock_enable_1 = K2_valid_rreq;
S1_q_b[0]_PORT_B_data_out = MEMORY(S1_q_b[0]_PORT_A_data_in_reg, , S1_q_b[0]_PORT_A_address_reg, S1_q_b[0]_PORT_B_address_reg, S1_q_b[0]_PORT_A_write_enable_reg, S1_q_b[0]_PORT_B_read_enable_reg, , , S1_q_b[0]_clock_0, S1_q_b[0]_clock_1, , S1_q_b[0]_clock_enable_1, , );
S1_q_b[0] = S1_q_b[0]_PORT_B_data_out[0];

--S1_q_b[7] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[7] at M512_X4_Y24
S1_q_b[0]_PORT_A_data_in = BUS(wb_dat_i[0], wb_dat_i[1], wb_dat_i[2], wb_dat_i[3], wb_dat_i[4], wb_dat_i[5], wb_dat_i[6], wb_dat_i[7]);
S1_q_b[0]_PORT_A_data_in_reg = DFFE(S1_q_b[0]_PORT_A_data_in, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[0]_PORT_A_address_reg = DFFE(S1_q_b[0]_PORT_A_address, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[0]_PORT_B_address_reg = DFFE(S1_q_b[0]_PORT_B_address, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_PORT_A_write_enable = K2L9;
S1_q_b[0]_PORT_A_write_enable_reg = DFFE(S1_q_b[0]_PORT_A_write_enable, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_read_enable = VCC;
S1_q_b[0]_PORT_B_read_enable_reg = DFFE(S1_q_b[0]_PORT_B_read_enable, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_clock_0 = GLOBAL(clk);
S1_q_b[0]_clock_1 = GLOBAL(clk);
S1_q_b[0]_clock_enable_1 = K2_valid_rreq;
S1_q_b[0]_PORT_B_data_out = MEMORY(S1_q_b[0]_PORT_A_data_in_reg, , S1_q_b[0]_PORT_A_address_reg, S1_q_b[0]_PORT_B_address_reg, S1_q_b[0]_PORT_A_write_enable_reg, S1_q_b[0]_PORT_B_read_enable_reg, , , S1_q_b[0]_clock_0, S1_q_b[0]_clock_1, , S1_q_b[0]_clock_enable_1, , );
S1_q_b[7] = S1_q_b[0]_PORT_B_data_out[7];

--S1_q_b[6] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[6] at M512_X4_Y24
S1_q_b[0]_PORT_A_data_in = BUS(wb_dat_i[0], wb_dat_i[1], wb_dat_i[2], wb_dat_i[3], wb_dat_i[4], wb_dat_i[5], wb_dat_i[6], wb_dat_i[7]);
S1_q_b[0]_PORT_A_data_in_reg = DFFE(S1_q_b[0]_PORT_A_data_in, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[0]_PORT_A_address_reg = DFFE(S1_q_b[0]_PORT_A_address, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[0]_PORT_B_address_reg = DFFE(S1_q_b[0]_PORT_B_address, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_PORT_A_write_enable = K2L9;
S1_q_b[0]_PORT_A_write_enable_reg = DFFE(S1_q_b[0]_PORT_A_write_enable, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_read_enable = VCC;
S1_q_b[0]_PORT_B_read_enable_reg = DFFE(S1_q_b[0]_PORT_B_read_enable, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_clock_0 = GLOBAL(clk);
S1_q_b[0]_clock_1 = GLOBAL(clk);
S1_q_b[0]_clock_enable_1 = K2_valid_rreq;
S1_q_b[0]_PORT_B_data_out = MEMORY(S1_q_b[0]_PORT_A_data_in_reg, , S1_q_b[0]_PORT_A_address_reg, S1_q_b[0]_PORT_B_address_reg, S1_q_b[0]_PORT_A_write_enable_reg, S1_q_b[0]_PORT_B_read_enable_reg, , , S1_q_b[0]_clock_0, S1_q_b[0]_clock_1, , S1_q_b[0]_clock_enable_1, , );
S1_q_b[6] = S1_q_b[0]_PORT_B_data_out[6];

--S1_q_b[5] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[5] at M512_X4_Y24
S1_q_b[0]_PORT_A_data_in = BUS(wb_dat_i[0], wb_dat_i[1], wb_dat_i[2], wb_dat_i[3], wb_dat_i[4], wb_dat_i[5], wb_dat_i[6], wb_dat_i[7]);
S1_q_b[0]_PORT_A_data_in_reg = DFFE(S1_q_b[0]_PORT_A_data_in, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[0]_PORT_A_address_reg = DFFE(S1_q_b[0]_PORT_A_address, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[0]_PORT_B_address_reg = DFFE(S1_q_b[0]_PORT_B_address, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_PORT_A_write_enable = K2L9;
S1_q_b[0]_PORT_A_write_enable_reg = DFFE(S1_q_b[0]_PORT_A_write_enable, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_read_enable = VCC;
S1_q_b[0]_PORT_B_read_enable_reg = DFFE(S1_q_b[0]_PORT_B_read_enable, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_clock_0 = GLOBAL(clk);
S1_q_b[0]_clock_1 = GLOBAL(clk);
S1_q_b[0]_clock_enable_1 = K2_valid_rreq;
S1_q_b[0]_PORT_B_data_out = MEMORY(S1_q_b[0]_PORT_A_data_in_reg, , S1_q_b[0]_PORT_A_address_reg, S1_q_b[0]_PORT_B_address_reg, S1_q_b[0]_PORT_A_write_enable_reg, S1_q_b[0]_PORT_B_read_enable_reg, , , S1_q_b[0]_clock_0, S1_q_b[0]_clock_1, , S1_q_b[0]_clock_enable_1, , );
S1_q_b[5] = S1_q_b[0]_PORT_B_data_out[5];

--S1_q_b[4] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[4] at M512_X4_Y24
S1_q_b[0]_PORT_A_data_in = BUS(wb_dat_i[0], wb_dat_i[1], wb_dat_i[2], wb_dat_i[3], wb_dat_i[4], wb_dat_i[5], wb_dat_i[6], wb_dat_i[7]);
S1_q_b[0]_PORT_A_data_in_reg = DFFE(S1_q_b[0]_PORT_A_data_in, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[0]_PORT_A_address_reg = DFFE(S1_q_b[0]_PORT_A_address, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[0]_PORT_B_address_reg = DFFE(S1_q_b[0]_PORT_B_address, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_PORT_A_write_enable = K2L9;
S1_q_b[0]_PORT_A_write_enable_reg = DFFE(S1_q_b[0]_PORT_A_write_enable, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_read_enable = VCC;
S1_q_b[0]_PORT_B_read_enable_reg = DFFE(S1_q_b[0]_PORT_B_read_enable, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_clock_0 = GLOBAL(clk);
S1_q_b[0]_clock_1 = GLOBAL(clk);
S1_q_b[0]_clock_enable_1 = K2_valid_rreq;
S1_q_b[0]_PORT_B_data_out = MEMORY(S1_q_b[0]_PORT_A_data_in_reg, , S1_q_b[0]_PORT_A_address_reg, S1_q_b[0]_PORT_B_address_reg, S1_q_b[0]_PORT_A_write_enable_reg, S1_q_b[0]_PORT_B_read_enable_reg, , , S1_q_b[0]_clock_0, S1_q_b[0]_clock_1, , S1_q_b[0]_clock_enable_1, , );
S1_q_b[4] = S1_q_b[0]_PORT_B_data_out[4];

--S1_q_b[3] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[3] at M512_X4_Y24
S1_q_b[0]_PORT_A_data_in = BUS(wb_dat_i[0], wb_dat_i[1], wb_dat_i[2], wb_dat_i[3], wb_dat_i[4], wb_dat_i[5], wb_dat_i[6], wb_dat_i[7]);
S1_q_b[0]_PORT_A_data_in_reg = DFFE(S1_q_b[0]_PORT_A_data_in, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[0]_PORT_A_address_reg = DFFE(S1_q_b[0]_PORT_A_address, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[0]_PORT_B_address_reg = DFFE(S1_q_b[0]_PORT_B_address, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_PORT_A_write_enable = K2L9;
S1_q_b[0]_PORT_A_write_enable_reg = DFFE(S1_q_b[0]_PORT_A_write_enable, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_read_enable = VCC;
S1_q_b[0]_PORT_B_read_enable_reg = DFFE(S1_q_b[0]_PORT_B_read_enable, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_clock_0 = GLOBAL(clk);
S1_q_b[0]_clock_1 = GLOBAL(clk);
S1_q_b[0]_clock_enable_1 = K2_valid_rreq;
S1_q_b[0]_PORT_B_data_out = MEMORY(S1_q_b[0]_PORT_A_data_in_reg, , S1_q_b[0]_PORT_A_address_reg, S1_q_b[0]_PORT_B_address_reg, S1_q_b[0]_PORT_A_write_enable_reg, S1_q_b[0]_PORT_B_read_enable_reg, , , S1_q_b[0]_clock_0, S1_q_b[0]_clock_1, , S1_q_b[0]_clock_enable_1, , );
S1_q_b[3] = S1_q_b[0]_PORT_B_data_out[3];

--S1_q_b[2] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[2] at M512_X4_Y24
S1_q_b[0]_PORT_A_data_in = BUS(wb_dat_i[0], wb_dat_i[1], wb_dat_i[2], wb_dat_i[3], wb_dat_i[4], wb_dat_i[5], wb_dat_i[6], wb_dat_i[7]);
S1_q_b[0]_PORT_A_data_in_reg = DFFE(S1_q_b[0]_PORT_A_data_in, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[0]_PORT_A_address_reg = DFFE(S1_q_b[0]_PORT_A_address, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[0]_PORT_B_address_reg = DFFE(S1_q_b[0]_PORT_B_address, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_PORT_A_write_enable = K2L9;
S1_q_b[0]_PORT_A_write_enable_reg = DFFE(S1_q_b[0]_PORT_A_write_enable, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_read_enable = VCC;
S1_q_b[0]_PORT_B_read_enable_reg = DFFE(S1_q_b[0]_PORT_B_read_enable, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_clock_0 = GLOBAL(clk);
S1_q_b[0]_clock_1 = GLOBAL(clk);
S1_q_b[0]_clock_enable_1 = K2_valid_rreq;
S1_q_b[0]_PORT_B_data_out = MEMORY(S1_q_b[0]_PORT_A_data_in_reg, , S1_q_b[0]_PORT_A_address_reg, S1_q_b[0]_PORT_B_address_reg, S1_q_b[0]_PORT_A_write_enable_reg, S1_q_b[0]_PORT_B_read_enable_reg, , , S1_q_b[0]_clock_0, S1_q_b[0]_clock_1, , S1_q_b[0]_clock_enable_1, , );
S1_q_b[2] = S1_q_b[0]_PORT_B_data_out[2];

--S1_q_b[1] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[1] at M512_X4_Y24
S1_q_b[0]_PORT_A_data_in = BUS(wb_dat_i[0], wb_dat_i[1], wb_dat_i[2], wb_dat_i[3], wb_dat_i[4], wb_dat_i[5], wb_dat_i[6], wb_dat_i[7]);
S1_q_b[0]_PORT_A_data_in_reg = DFFE(S1_q_b[0]_PORT_A_data_in, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[0]_PORT_A_address_reg = DFFE(S1_q_b[0]_PORT_A_address, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_address = BUS(E6_safe_q[0], E6_safe_q[1], E6_safe_q[2], E6_safe_q[3]);
S1_q_b[0]_PORT_B_address_reg = DFFE(S1_q_b[0]_PORT_B_address, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_PORT_A_write_enable = K2L9;
S1_q_b[0]_PORT_A_write_enable_reg = DFFE(S1_q_b[0]_PORT_A_write_enable, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_read_enable = VCC;
S1_q_b[0]_PORT_B_read_enable_reg = DFFE(S1_q_b[0]_PORT_B_read_enable, S1_q_b[0]_clock_1, , , S1_q_b[0]_clock_enable_1);
S1_q_b[0]_clock_0 = GLOBAL(clk);
S1_q_b[0]_clock_1 = GLOBAL(clk);
S1_q_b[0]_clock_enable_1 = K2_valid_rreq;
S1_q_b[0]_PORT_B_data_out = MEMORY(S1_q_b[0]_PORT_A_data_in_reg, , S1_q_b[0]_PORT_A_address_reg, S1_q_b[0]_PORT_B_address_reg, S1_q_b[0]_PORT_A_write_enable_reg, S1_q_b[0]_PORT_B_read_enable_reg, , , S1_q_b[0]_clock_0, S1_q_b[0]_clock_1, , S1_q_b[0]_clock_enable_1, , );
S1_q_b[1] = S1_q_b[0]_PORT_B_data_out[1];


--E5_safe_q[3] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[3] at LC_X7_Y29_N8
--operation mode is normal

E5_safe_q[3]_lut_out = E5L71 $ E5_safe_q[3];
E5_safe_q[3] = DFFEA(E5_safe_q[3]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , K2L1, , );


--E5_safe_q[2] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[2] at LC_X7_Y29_N7
--operation mode is arithmetic

E5_safe_q[2]_lut_out = E5_safe_q[2] $ !E5L41;
E5_safe_q[2] = DFFEA(E5_safe_q[2]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , K2L1, , );

--E5L71 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[2]~COUT0 at LC_X7_Y29_N7
--operation mode is arithmetic

E5L71_cout_0 = !E5L41 & (K2L9 $ !E5_safe_q[2]);
E5L71 = CARRY(E5L71_cout_0);

--E5L81 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[2]~COUT1 at LC_X7_Y29_N7
--operation mode is arithmetic

E5L81_cout_1 = !E5L51 & (K2L9 $ !E5_safe_q[2]);
E5L81 = CARRY(E5L81_cout_1);


--E5_safe_q[1] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[1] at LC_X7_Y29_N6
--operation mode is arithmetic

E5_safe_q[1]_lut_out = E5_safe_q[1] $ E5L11;
E5_safe_q[1] = DFFEA(E5_safe_q[1]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , K2L1, , );

--E5L41 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[1]~COUT0 at LC_X7_Y29_N6
--operation mode is arithmetic

E5L41_cout_0 = K2L9 $ E5_safe_q[1] # !E5L11;
E5L41 = CARRY(E5L41_cout_0);

--E5L51 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[1]~COUT1 at LC_X7_Y29_N6
--operation mode is arithmetic

E5L51_cout_1 = K2L9 $ E5_safe_q[1] # !E5L21;
E5L51 = CARRY(E5L51_cout_1);


--E5_safe_q[0] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0] at LC_X7_Y29_N5
--operation mode is arithmetic

E5_safe_q[0]_lut_out = !E5_safe_q[0];
E5_safe_q[0] = DFFEA(E5_safe_q[0]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , K2L1, , );

--E5L11 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0]~COUT0 at LC_X7_Y29_N5
--operation mode is arithmetic

E5L11_cout_0 = K2L9 $ !E5_safe_q[0];
E5L11 = CARRY(E5L11_cout_0);

--E5L21 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0]~COUT1 at LC_X7_Y29_N5
--operation mode is arithmetic

E5L21_cout_1 = K2L9 $ !E5_safe_q[0];
E5L21 = CARRY(E5L21_cout_1);


--A1L631 is i~159 at LC_X25_Y29_N2
--operation mode is arithmetic

A1L631 = !dl[0];

--A1L831 is i~159COUT0 at LC_X25_Y29_N2
--operation mode is arithmetic

A1L831_cout_0 = dl[0];
A1L831 = CARRY(A1L831_cout_0);

--A1L931 is i~159COUT1 at LC_X25_Y29_N2
--operation mode is arithmetic

A1L931_cout_1 = dl[0];
A1L931 = CARRY(A1L931_cout_1);


--A1L041 is i~160 at LC_X25_Y29_N3
--operation mode is arithmetic

A1L041 = dl[1] $ !A1L831;

--A1L241 is i~160COUT0 at LC_X25_Y29_N3
--operation mode is arithmetic

A1L241_cout_0 = !dl[1] & !A1L831;
A1L241 = CARRY(A1L241_cout_0);

--A1L341 is i~160COUT1 at LC_X25_Y29_N3
--operation mode is arithmetic

A1L341_cout_1 = !dl[1] & !A1L931;
A1L341 = CARRY(A1L341_cout_1);


--A1L441 is i~161 at LC_X25_Y29_N4
--operation mode is arithmetic

A1L441 = dl[2] $ A1L241;

--A1L541 is i~161COUT at LC_X25_Y29_N4
--operation mode is arithmetic

A1L541 = CARRY(dl[2] # !A1L341);


--A1L641 is i~162 at LC_X25_Y29_N5
--operation mode is arithmetic

A1L641_carry_eqn = A1L541;
A1L641 = dl[3] $ !A1L641_carry_eqn;

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