** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC29 QOUT0
        | +------------- LC25 QOUT1
        | | +----------- LC24 QOUT2
        | | | +--------- LC23 QOUT3
        | | | | +------- LC22 QOUT4
        | | | | | +----- LC20 QOUT5
        | | | | | | +--- LC17 QOUT6
        | | | | | | | +- LC21 QOUT7
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC29 -> * * - - - - - - | - * | <-- QOUT0
LC25 -> * * * - - - - - | - * | <-- QOUT1
LC24 -> - * * * - - - - | - * | <-- QOUT2
LC23 -> - - * * - - - * | - * | <-- QOUT3
LC22 -> * - - - * * - - | - * | <-- QOUT4
LC20 -> - - - - * * * - | - * | <-- QOUT5
LC17 -> - - - - - * * * | - * | <-- QOUT6
LC21 -> - - - - - - * * | - * | <-- QOUT7

Pin
43   -> - - - - - - - - | - - | <-- CLK
14   -> * - - - - - - - | - * | <-- DATA0
17   -> - * - - - - - - | - * | <-- DATA1
16   -> - - * - - - - - | - * | <-- DATA2
13   -> - - - * - - - - | - * | <-- DATA3
12   -> - - - - * - - - | - * | <-- DATA4
11   -> - - - - - * - - | - * | <-- DATA5
9    -> - - - - - - * - | - * | <-- DATA6
8    -> - - - - - - - * | - * | <-- DATA7
7    -> * * * * * * * * | - * | <-- MODE0
6    -> * * * * * * * * | - * | <-- MODE1
1    -> - - - - - - - - | - - | <-- RESET
4    -> - - - * - - - - | - * | <-- SHIFTER_LEFT
5    -> - - - - * - - - | - * | <-- SHIFTER_RIGHT


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                         e:\shiftergdf\shifter.rpt
shifter

** EQUATIONS **

CLK      : INPUT;
DATA0    : INPUT;
DATA1    : INPUT;
DATA2    : INPUT;
DATA3    : INPUT;
DATA4    : INPUT;
DATA5    : INPUT;
DATA6    : INPUT;
DATA7    : INPUT;
MODE0    : INPUT;
MODE1    : INPUT;
RESET    : INPUT;
SHIFTER_LEFT : INPUT;
SHIFTER_RIGHT : INPUT;

-- Node name is 'QOUT0' = '|74194:25|QA' 
-- Equation name is 'QOUT0', type is output 
 QOUT0   = DFFE( _EQ001 $  GND, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ001 =  DATA0 &  MODE0 &  MODE1
         #  MODE0 & !MODE1 &  QOUT4
         # !MODE0 &  MODE1 &  QOUT1
         # !MODE0 & !MODE1 &  QOUT0;

-- Node name is 'QOUT1' = '|74194:25|QB' 
-- Equation name is 'QOUT1', type is output 
 QOUT1   = DFFE( _EQ002 $  GND, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ002 =  DATA1 &  MODE0 &  MODE1
         #  MODE0 & !MODE1 &  QOUT0
         # !MODE0 &  MODE1 &  QOUT2
         # !MODE0 & !MODE1 &  QOUT1;

-- Node name is 'QOUT2' = '|74194:25|QC' 
-- Equation name is 'QOUT2', type is output 
 QOUT2   = DFFE( _EQ003 $  GND, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ003 =  DATA2 &  MODE0 &  MODE1
         #  MODE0 & !MODE1 &  QOUT1
         # !MODE0 &  MODE1 &  QOUT3
         # !MODE0 & !MODE1 &  QOUT2;

-- Node name is 'QOUT3' = '|74194:25|QD' 
-- Equation name is 'QOUT3', type is output 
 QOUT3   = DFFE( _EQ004 $  GND, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ004 =  DATA3 &  MODE0 &  MODE1
         #  MODE0 & !MODE1 &  QOUT2
         # !MODE0 &  MODE1 &  SHIFTER_LEFT
         # !MODE0 & !MODE1 &  QOUT3;

-- Node name is 'QOUT4' = '|74194:1|QA' 
-- Equation name is 'QOUT4', type is output 
 QOUT4   = DFFE( _EQ005 $  GND, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ005 =  DATA4 &  MODE0 &  MODE1
         #  MODE0 & !MODE1 &  SHIFTER_RIGHT
         # !MODE0 &  MODE1 &  QOUT5
         # !MODE0 & !MODE1 &  QOUT4;

-- Node name is 'QOUT5' = '|74194:1|QB' 
-- Equation name is 'QOUT5', type is output 
 QOUT5   = DFFE( _EQ006 $  GND, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ006 =  DATA5 &  MODE0 &  MODE1
         #  MODE0 & !MODE1 &  QOUT4
         # !MODE0 &  MODE1 &  QOUT6
         # !MODE0 & !MODE1 &  QOUT5;

-- Node name is 'QOUT6' = '|74194:1|QC' 
-- Equation name is 'QOUT6', type is output 
 QOUT6   = DFFE( _EQ007 $  GND, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ007 =  DATA6 &  MODE0 &  MODE1
         #  MODE0 & !MODE1 &  QOUT5
         # !MODE0 &  MODE1 &  QOUT7
         # !MODE0 & !MODE1 &  QOUT6;

-- Node name is 'QOUT7' = '|74194:1|QD' 
-- Equation name is 'QOUT7', type is output 
 QOUT7   = DFFE( _EQ008 $  GND, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ008 =  DATA7 &  MODE0 &  MODE1
         #  MODE0 & !MODE1 &  QOUT6
         # !MODE0 &  MODE1 &  QOUT3
         # !MODE0 & !MODE1 &  QOUT7;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                  e:\shiftergdf\shifter.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,181K