?? shifter.vhd
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHIFTER IS
PORT(DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SHIFT_LEFT:IN STD_LOGIC;
SHIFT_RIGHT:IN STD_LOGIC;
RESET:IN STD_LOGIC;
MODE:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK:IN STD_LOGIC;
QOUT:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0));
END SHIFTER;
ARCHITECTURE ART OF SHIFTER IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL(RISING_EDGE(CLK));
IF(RESET='0')THEN
QOUT<="00000000";
ELSE
CASE MODE IS
WHEN "01"=>QOUT<=SHIFT_RIGHT&QOUT(7 DOWNTO 1);
WHEN "10"=>QOUT<=QOUT(6 DOWNTO 0)&SHIFT_LEFT;
WHEN "11"=>QOUT<=DATA;
WHEN OTHERS=>NULL;
END CASE;
END IF;
END PROCESS;
END ART;
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