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?? power scripts for i8051 synthesizable model.htm

?? 8051的IP,采用VHDL語言描述,支持intel的HEX格式,包括中斷,定時器等.
?? HTM
字號:
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<HTML><HEAD><TITLE>Power Scripts for i8051 Synthesizable Model</TITLE>
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<TABLE width=640>
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    <TD>
      <H1>Tuning Environment for i8051 Synthesizable Model</H1>
      <H2>Introduction</H2>
      <P>One of the defining characteristics of embedded systems is that they 
      run one application for their entire execution time. This characteristic 
      creates a great potential for optimizations. For example, a general 
      purpose processor might have a datapath consisting of a register file, 
      ALU, and a shifter. For an instruction such as a move, this datapath is 
      expensive in terms of power because it must pass through the ALU and 
      shifter before being written back into the register file. If this move 
      operation was very common to a particular application, an optimization 
      could be made by modifying the register file to move data from one 
      location to another. 
      <P>The information on this page describes an environment that simplifies 
      the process of tuning a microprocessor. Three main tools are provided in 
      order to analyze the power consumption of an 8051 microprocessor. The 
      first of these tools is an architectural view which generates a 
      hierarchical display of power consumption throughout the components of the 
      processor. The output is formatted so that it is readable by xdu, a 
      graphical program for displaying tree structures. The second tool 
      calculates the average power per instruction for the entire instruction 
      set (several jump instructions have not yet been implemented in this 
      tool). The third tool is an instruction set simulator which outputs a 
      program memory view that displays the instruction, power, and frequency 
      for every address. It also provides a data memory view that calculates 
      accesses for each location in ram. <BR><BR>
      <HR>
      <BR>
      <H2>Example</H2>After running the initial version of the 8051, we obtained 
      the following results: <BR><BR>The table below shows a small sample of the 
      output of the instruction set power tool. The actual output shows results 
      for all instructions excluding several jumps which have not been 
      implemented yet. <BR><BR><I>(Small sample of instruction set power, all 
      values are in mW)</I><BR>
      <TABLE border=2>
        <TBODY>
        <TR>
          <TD>ADDC_1</TD>
          <TD>31.526465034965</TD></TR>
        <TR>
          <TD>ADDC_2</TD>
          <TD>38.1159</TD></TR>
        <TR>
          <TD>ADDC_3</TD>
          <TD>31.9229685314685</TD></TR>
        <TR>
          <TD>ADDC_4</TD>
          <TD>43.3595</TD></TR>
        <TR>
          <TD>ADD_1</TD>
          <TD>31.6965116550117</TD></TR>
        <TR>
          <TD>ADD_2</TD>
          <TD>33.2728333333333</TD></TR>
        <TR>
          <TD>ADD_3</TD>
          <TD>32.8297284382284</TD></TR>
        <TR>
          <TD>ADD_4</TD>
          <TD>41.2952333333333</TD></TR></TBODY></TABLE><BR><BR>The image below 
      shows the output from the architectural view tool. It can be seen that 
      U_RAM, U_ALU, U_CTR, and the buses for RAM and ROM are the most expensive 
      components. Xdu allows you to explore this hierarchy in much more detail 
      than is shown in the image. <BR><BR><I>(Architectural view tool output 
      displayed in xdu, values are in 1/1000mW)</I> <BR><IMG 
      src="Power Scripts for i8051 Synthesizable Model.files/xdu1.jpeg"> 
      <BR><BR>The table below displays output from the program memory view that 
      is provided by the instruction set simulation tool. For every location in 
      program memory, it displays the address, instruction, frequency of 
      execution, average power, and power * frequency. This view makes it easy 
      to determine which area of the program is the bottleneck in terms of power 
      consumption. <BR><BR><I>(Small sample of program memory view, power is in 
      mW)</I> 
      <TABLE border=2>
        <TBODY>
        <TR>
          <TD>Addr</TD>
          <TD>Ins</TD>
          <TD>Freq</TD>
          <TD>Pwr</TD>
          <TD>Pwr*Frq</TD></TR>
        <TR>
          <TD>00727</TD>
          <TD>XCH_1</TD>
          <TD>15901</TD>
          <TD>4.78177</TD>
          <TD>76034.9</TD></TR>
        <TR>
          <TD>00728</TD>
          <TD>XCH_1</TD>
          <TD>15901</TD>
          <TD>4.78177</TD>
          <TD>76034.9</TD></TR>
        <TR>
          <TD>00729</TD>
          <TD>RRC</TD>
          <TD>15901</TD>
          <TD>3.86277</TD>
          <TD>61421.9</TD></TR>
        <TR>
          <TD>00730</TD>
          <TD>XCH_1</TD>
          <TD>15901</TD>
          <TD>4.78177</TD>
          <TD>76034.9</TD></TR>
        <TR>
          <TD>00731</TD>
          <TD>INC_1</TD>
          <TD>16474</TD>
          <TD>3.90566</TD>
          <TD>64341.9</TD></TR>
        <TR>
          <TD>00732</TD>
          <TD>JNZ</TD>
          <TD>16474</TD>
          <TD>0</TD>
          <TD>0</TD></TR></TBODY></TABLE><BR><BR>A small sample of ram accesses are 
      shown below. It is obvious in this that the example most frequently 
      locations are the accumulator and psw. <BR><BR><I>(Small sample of ram 
      location frequencies)</I><BR>
      <TABLE border=2>
        <TBODY>
        <TR>
          <TD>Addr</TD>
          <TD>Freq</TD>
          <TD>Type</TD></TR>
        <TR>
          <TD>00000</TD>
          <TD>32557</TD>
          <TD>RegBank0</TD></TR>
        <TR>
          <TD>00001</TD>
          <TD>32334</TD>
          <TD>RegBank0</TD></TR>
        <TR>
          <TD>00002</TD>
          <TD>27461</TD>
          <TD>RegBank0</TD></TR>
        <TR>
          <TD>00003</TD>
          <TD>30042</TD>
          <TD>RegBank0</TD></TR>
        <TR>
          <TD>00004</TD>
          <TD>101096</TD>
          <TD>RegBank0</TD></TR>
        <TR>
          <TD>00005</TD>
          <TD>103961</TD>
          <TD>RegBank0</TD></TR>
        <TR>
          <TD>00006</TD>
          <TD>94789</TD>
          <TD>RegBank0</TD></TR>
        <TR>
          <TD>00007</TD>
          <TD>116525</TD>
          <TD>RegBank0</TD></TR>
        <TR>
          <TD>00336</TD>
          <TD>939913</TD>
          <TD>PSW</TD></TR>
        <TR>
          <TD>00352</TD>
          <TD>1003559</TD>
          <TD>ACC</TD></TR>
        <TR>
          <TD>00368 </TD>
          <TD>11015</TD>
          <TD>B</TD></TR></TBODY></TABLE><BR>
      <HR>

      <H2>Installation Instructions</H2><I>(All files should be downloaded into 
      the same directory)</I> <BR>1) Download <A 
      href="http://www.cs.ucr.edu/~dalton/i8051/i8051powerweb/i8051pwranalysis.tgz">i8051pwranalysis.tgz</A>.<BR>2) 
      Download <A 
      href="http://www.cs.ucr.edu/~dalton/i8051/i8051powerweb/xdu-3_0_tar">Xdu</A> 
      for graphical tree representations. <BR>3) Download <A 
      href="http://www.cs.ucr.edu/~dalton/i8051/i8051powerweb/install.scr">install.scr</A>.<BR>4) 
      Run install.scr.<BR>5) The sample output is located in the following 
      locations:<BR>Architectural view =&gt; ph_results/*.xdu<BR>Instruction set 
      power =&gt; inspower.txt<BR>Program memory view =&gt; 
      iss_results/*.pmp<BR>Data memory view =&gt; iss_results/*.ram<BR>
      <H2>Execution Instructions</H2>1) In order to run all tools and generate a 
      report, run all.pl [version]. [Version] is used to print a version name on 
      the generated report. All scripts are located in the i8051pwranalysis 
      directory. <BR>2) The xdu executable is in the xdu directory. It can be 
      used on all files in the i8051pwranalysis directory that have a .xdu file 
      extension. <BR>3) <A 
      href="http://www.cs.ucr.edu/~dalton/i8051/i8051powerweb/tools.html">Individual 
      tools and scripts are described in detail at this link.</A> 
</TD></TR></TBODY></TABLE></BODY></HTML>

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