# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# OverwriteFiles = True
# Core name: buffer_comp_chrom
# Number of Primitives in design: 2
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 0
# Number of LUTs used in design: 0
# Number of REG used in design: 0
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 2
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET SimulationOutputProducts = VHDL
SET XilinxFamily = Virtex2
SET OutputOption = DesignFlow
SET DesignFlow = VHDL
SET FlowVendor = Other
SET FormalVerification = None
SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0
CSET primitive_selection = Optimize_For_Area
CSET init_value = 0
CSET register_inputs = false
CSET write_enable_polarity = Active_High
CSET init_pin = false
CSET initialization_pin_polarity = Active_High
CSET global_init_value = 0
CSET select_primitive = 16kx1
CSET enable_pin = false
CSET write_mode = Read_Before_Write
CSET port_configuration = Read_And_Write
CSET component_name = buffer_comp_chrom
CSET active_clock_edge = Rising_Edge_Triggered
CSET handshaking_pins = false
CSET width = 12
CSET load_init_file = false
CSET enable_pin_polarity = Active_High
CSET additional_output_pipe_stages = 0
CSET has_limit_data_pitch = false
CSET limit_data_pitch = 18
CSET depth = 1408
GENERATE