# Xilinx CORE Generator 6.1i
SELECT 2-D_Discrete_Cosine_Transform Virtex2 Xilinx,_Inc. 2.0
CSET input_data_width = 8
CSET precision_control = Round
CSET result_width = 19
CSET enable_symmetry = true
CSET operation = Forward_DCT
CSET internal_width = 19
CSET input_data_type = Signed
CSET coefficient_width = 24
CSET has_reset = false
CSET component_name = dct2d
CSET transpose_memory = Block
CSET clock_cycles_per_input_sample = 9
GENERATE