# Xilinx CORE Generator 6.1i
SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0
CSET primitive_selection = Optimize_For_Area
CSET init_value = 0
CSET register_inputs = false
CSET write_enable_polarity = Active_High
CSET init_pin = false
CSET initialization_pin_polarity = Active_High
CSET global_init_value = 0
CSET select_primitive = 16kx1
CSET enable_pin = false
CSET write_mode = Read_After_Write
CSET port_configuration = Read_And_Write
CSET component_name = buffer_img
CSET active_clock_edge = Rising_Edge_Triggered
CSET handshaking_pins = false
CSET width = 8
CSET load_init_file = true
CSET enable_pin_polarity = Active_High
CSET additional_output_pipe_stages = 0
CSET coefficient_file = E:\VHDL\PFCarrera\FPGA\Coregen\buffer_img.coe
CSET has_limit_data_pitch = false
CSET limit_data_pitch = 18
CSET depth = 51200
GENERATE