//-------------------------------------------------------------------------------------
//
// Author: John Clayton
// Date  : June 25, 2001
// Update: 6/25/01 copied this file from ps2_mouse.v (pared down).
// Update: 6/07/01 Finished initial coding efforts.
// Update: 7/19/01 First compilation.  Added master_br_o and master_bg_i;
// Update: 7/25/01 Testing.  Eliminated msg_active signal.  Changed serial.v
//                 to reflect new handshaking (i.e. "load_request" is now a
//                 periodic pulse of tx_clk_1x from rs232_tx...)
// Update: 7/30/01 Began coding m2 state machine.  Defined response codes.
// Update: 8/01/01 After some testing with m2, merged m2 into m1.  Eliminated
//                 response codes.
// Update: 8/02/01 Tested & measured the single "combined" state machine's
//                 performance, and "it was found wanting."  (The 49.152MHz
//                 clock frequency was too fast for it...)  Created clk_s
//                 at 49.152/2 MHz, and this worked.
// Update: 8/03/01 Added counter loop to "execute" and "bus_granted" states
//                 so that multiple bus cycles are generated, at sequential
//                 addresses.  However, the qty field is not cleared before
//                 being loaded with new characters, which causes problems.
// Update: 8/07/01 Finished debugging.  The read print formatting is now
//                 correct, and the unit appears to operate correctly.
//                 Many hours were spent puzzling over how to make this work.
//                 Removed port "debug".
// Update: 8/24/01 Added "master_stb_i" and "master_we_i" inputs and logic.
// Update: 12/13/01 For memory_sizer.v, I lowered the frequency of clk_s down
//                 to 49.152/4 MHz, so I changed the CLOCK_FACTOR from 8 to 4
//                 on the rs232 transciever, and this worked fine.
//
//
//
//
//
// Description
//-------------------------------------------------------------------------------------
// This is a state-machine driven rs232 serial port interface to a "Wishbone"
// type of bus.  It is intended to be used as a "Wishbone system controller"
// for debugging purposes.  Specifically, the unit allows the user to send
// text commands to the "rs232_syscon" unit, in order to generate read and
// write cycles on the Wishbone compatible bus.  The command structure is
// quite terse and spartan in nature, this is for the sake of the logic itself.
// Because the menu-driven command structure is supported without the use of
// dedicated memory blocks (in order to maintain cross-platform portability
// as much as possible) the menus and command responses were kept as small
// as possible.  In most cases, the responses from the unit to the user
// consist of a "newline" and one or two visible characters.  The command
// structure consists of the following commands and responses:
//
// Command Syntax              Purpose
// ---------------             ---------------------------------------
// w aaaa dddd xx              Write data "dddd" starting at address "aaaa"
//                             perform this "xx" times at sequential addresses.
//                             (The quantity field is optional, default is 1).
// r aaaa xx                   Read data starting from address "aaaa."
//                             Perform this "xx" times at sequential addresses.
//                             (The quantity field is optional, default is 1).
// i                           Send a reset pulse to the system. (initialize).
//
// Response from rs232_syscon  Meaning
// --------------------------  ---------------------------------------
// OK                          Command received and performed.  No errors.
// ?                           Command buffer full, without receiving "enter."
// C?                          Command not recognized.
// A?                          Address field syntax error.
// D?                          Data field syntax error.
// Q?                          Quantity field syntax error.
// !                           No "ack_i", or else "err_i" received from bus.
// B!                          No "bg_i" received from master.
//
// NOTES on the operation of this unit:
//
// - The unit generates a command prompt which is "-> ".
// - Capitalization is not important.
// - Each command is terminated by the "enter" key (0x0d character).
//   Commands are executed as soon as "enter" is received.
// - Trailing parameters need not be re-entered.  Their values will
//   remain the same as their previous settings.
// - Use of the backspace key is supported, so mistakes can be corrected.
// - The length of the command line is limited to a fixed number of
//   characters, as configured by parameter.
// - Fields are separated by white space, including "tab" and/or "space"
// - All numerical fields are interpreted as hexadecimal numbers.
//   Decimal is not supported.
// - Numerical field values are retained between commands.  If a "r" is issued
//   without any fields following it, the previous values will be used.  A
//   set of "quantity" reads will take place at sequential addresses.
//   If a "w" is issued without any fields following it, the previous data
//   value will be written "quantity" times at sequential addresses, starting
//   from the next location beyond where the last command ended.
// - If the user does not wish to use "ack" functionality, simply tie the
//   "ack_i" input to 1b'1, and then the ! response will never be generated.
// - The data which is read in by the "r" command is displayed using lines
//   which begin with the address, followed by the data fields.  The number
//   of data fields displayed per line (following the address) is adjustable
//   by setting a parameter.  No other display format adjustments can be made.
// - There is currently only a single watchdog timer.  It begins to count at
//   the time a user hits "enter" to execute a command.  If the bus is granted
//   and the ack is received before the expiration of the timer, then the
//   cycle will complete normally.  Therefore, the watchdog timeout value
//   needs to include time for the request and granting of the bus, in
//   addition to the time needed for the actual bus cycle to complete.
//
//
// Currently, there is only a single indicator (stb_o) generated during bus
// output cycles which are generated from this unit.
// The user can easily implement decoding logic based upon adr_o and stb_o
// which would serve as multiple "stb_o" type signals for different cores
// which would be sharing the same bus.
//
// The dat_io bus supported by this module is a tri-state type of bus.  The
// Wishbone spec. allows for this type of bus (see Wishbone spec. pg. 66).
// However, if separate dat_o and dat_i busses are desired, they can be added
// to the module without too much trouble.  Supposedly the only difference
// between the two forms of data bus is that one of them avoids using tri-state
// at the cost of doubling the number of interconnects used to carry data back
// and forth...  Some people say that tri-state should be avoided for use
// in internal busses in ASICs.  Maybe they are right.
// But in FPGAs tri-state seems to work pretty well, even for internal busses.
//
// Parameters are provided to configure the width of the different command
// fields.  To simplify the logic for binary to hexadecimal conversion, these
// parameters allow adjustment in units of 1 hex digit, not anything smaller.
// If your bus has 10 bits, for instance, simply set the address width to 3
// which produces 12 bits, and then just don't use the 2 msbs of address
// output.
//
// No support for the optional Wishbone "retry" (rty_i) input is provided at
// this time.
// No support for "tagn_o" bits is provided at this time, although a register
// might be added external to this module in order to implement to tag bits.
// No BLOCK or RMW cycles are supported currently, so cyc_o is equivalent to
// stb_o...
// The output busses are not tri-stated.  The user may add tri-state buffers
// external to the module, using "stb_o" to enable the buffer outputs.
//
//-------------------------------------------------------------------------------------


`define NIBBLE_SIZE 4        // Number of bits in one nibble

// The command register has these values
`define CMD_0 0              // Unused command
`define CMD_I 1              // Initialize (or reset)
`define CMD_R 2              // Read
`define CMD_W 3              // Write

module rs232_syscon (
  clk_i,
  reset_i,
  ack_i,
  err_i,
  master_bg_i,
  master_adr_i,
  master_stb_i,
  master_we_i,
  rs232_rxd_i,
  dat_io,
  rst_o,
  master_br_o,
  stb_o,
  cyc_o,
  adr_o,
  we_o,
  rs232_txd_o
  );


// Parameters

// The timer value can be from [0 to (2^WATCHDOG_TIMER_BITS_PP)-1] inclusive.
// RD_FIELDS_PP can be from [0 to (2^RD_FIELD_CTR_BITS_PP)-1] inclusive.
// Ensure that (2^CHAR_COUNT_BITS_PP) >= CMD_BUFFER_SIZE_PP.
// The setting of CMD_BUFFER_SIZE_PP should be large enough to hold the
// largest command, obviously.
// Ensure that (2^RD_DIGIT_COUNT_BITS_PP) is greater than or equal to the
//     larger of {ADR_DIGITS_PP,DAT_DIGITS_PP}.
parameter ADR_DIGITS_PP = 4;             // # of hex digits for address.
parameter DAT_DIGITS_PP = 4;             // # of hex digits for data.
parameter QTY_DIGITS_PP = 2;             // # of hex digits for quantity.
parameter CMD_BUFFER_SIZE_PP = 32;       // # of chars in the command buffer.
parameter CMD_PTR_BITS_PP = 4;           // # of Bits in command buffer ptr.
parameter WATCHDOG_TIMER_VALUE_PP = 200; // # of sys_clks before ack expected.
parameter WATCHDOG_TIMER_BITS_PP  = 8;   // # of bits needed for timer.
parameter RD_FIELDS_PP = 8;              // # of fields/line (when qty > 1).
parameter RD_FIELD_COUNT_BITS_PP = 3;    // # of bits in the fields counter.
parameter RD_DIGIT_COUNT_BITS_PP = 2;    // # of bits in the digits counter.


// State encodings, provided as parameters
// for flexibility to the one instantiating the module.
// In general, the default values need not be changed.

// There is one state machines: m1.
// "default" state upon power-up and configuration is:
//    "m1_initial_state"

parameter m1_initial_state = 5'h00;
parameter m1_send_ok = 5'h01;                    // Sends OK
parameter m1_send_prompt = 5'h02;                // Sends "-> "
parameter m1_check_received_char = 5'h03;
parameter m1_send_crlf = 5'h04;                  // Sends cr,lf
parameter m1_parse_error_indicator_crlf = 5'h05; // Sends cr,lf
parameter m1_parse_error_indicator = 5'h06;      // Sends ?
parameter m1_ack_error_indicator = 5'h07;        // Sends !
parameter m1_bg_error_indicator = 5'h08;         // Sends B!
parameter m1_cmd_error_indicator = 5'h09;        // Sends C?
parameter m1_adr_error_indicator = 5'h0a;        // Sends A?
parameter m1_dat_error_indicator = 5'h0b;        // Sends D?
parameter m1_qty_error_indicator = 5'h0c;        // Sends Q?
parameter m1_scan_command = 5'h10;
parameter m1_scan_adr_whitespace = 5'h11;
parameter m1_get_adr_field = 5'h12;
parameter m1_scan_dat_whitespace = 5'h13;
parameter m1_get_dat_field = 5'h14;
parameter m1_scan_qty_whitespace = 5'h15;
parameter m1_get_qty_field = 5'h16;
parameter m1_start_execution = 5'h17;
parameter m1_request_bus = 5'h18;
parameter m1_bus_granted = 5'h19;
parameter m1_execute = 5'h1a;
parameter m1_rd_send_adr_sr = 5'h1b;
parameter m1_rd_send_separator = 5'h1c;
parameter m1_rd_send_dat_sr = 5'h1d;
parameter m1_rd_send_space = 5'h1e;
parameter m1_rd_send_crlf = 5'h1f;

// I/O declarations
input clk_i;                 // System clock input
input reset_i;               // Reset signal for this module
input ack_i;                 // Ack input from Wishbone "slaves"
input err_i;                 // Err input from Wishbone "slaves"
input master_bg_i;           // Bus Grant (grants this module the bus)
                             // Address bus input from "normal" Wishbone
                             // master (i.e. from processor)
input [`NIBBLE_SIZE*ADR_DIGITS_PP-1:0] master_adr_i;
input master_stb_i;          // bus cycle signal from "normal" bus master
input master_we_i;           // write enable from "normal" bus master
input rs232_rxd_i;           // Serial data from debug host terminal.
                             // Data bus (tri-state, to save interconnect)
inout [`NIBBLE_SIZE*DAT_DIGITS_PP-1:0] dat_io;

output rst_o;                // Rst output to Wishbone "slaves"
output master_br_o;          // Bus request to normal master device.
output stb_o;                // Bus cycle indicator to Wishbone "slaves"
output cyc_o;                // Bus cycle indicator to Wishbone "slaves"
                             // Address bus output to Wishbone "slaves"
output [`NIBBLE_SIZE*ADR_DIGITS_PP-1:0] adr_o;
output we_o;                 // Write enable to Wishbone "slaves"
output rs232_txd_o;          // Serial transmit data to debug host terminal

reg rst_o;
reg master_br_o;

// Internal signal declarations
wire watchdog_timer_done;   // High when watchdog timer is expired
wire rd_addr_field_done;    // High when displayed addr field is complete
wire rd_data_field_done;    // High when displayed data field is complete
wire rd_line_done;          // High when displayed line is complete
wire char_is_enter;         // High when cmd_buffer[char_count] is enter.
wire char_is_whitespace;    // High when cmd_buffer[char_count] is whitespace.
wire char_is_num;           // High when cmd_buffer[char_count] is 0..9
wire char_is_a_f;           // High when cmd_buffer[char_count] is a..f
wire char_is_hex;           // High when cmd_buffer[char_count] is a hex char.
wire char_is_r;             // High when cmd_buffer[char_count] is r.
wire char_is_w;             // High when cmd_buffer[char_count] is w.
wire char_is_i;             // High when cmd_buffer[char_count] is i.
wire rx_char_is_enter;      // High when rs232_rx_char is enter.
wire rx_char_is_backspace;  // High when rs232_rx_char is backspace.
wire [4:0] msg_pointer;     // Determines message position or address.
wire [3:0] hex_digit;       // This is the digit to be stored.

reg rs232_echo;           // High == echo char's received.
reg [7:0] msg_char;       // Selected response message character.
reg [4:0] msg_base;       // Added to msg_offset to form msg_pointer.
reg [4:0] msg_offset;     // Offset from start of message.
reg reset_msg_offset;     // High == set message offset to zero
reg incr_msg_offset;      // Used for output messages.
reg cmd_i;                // Sets command.
reg cmd_r;                // Sets command.
reg cmd_w;                // Sets command.
reg shift_rd_adr;         // Shifts the rd_adr_sr by one character.
reg store_adr;            // Allows adr_sr to store hex_digit.
reg store_dat;            // Allows dat_sr to store hex_digit.
reg store_qty;            // Allows qty_sr to store hex_digit.
reg reset_adr;            // Clears adr_sr
reg reset_dat;            // Clears dat_sr
reg reset_qty;            // Clears qty_sr
reg init_qty;             // Sets qty_sr to 1
reg capture_dat;          // Puts dat_io into dat_sr for later display.

    // For the buses
wire [`NIBBLE_SIZE*ADR_DIGITS_PP-1:0] adr_ptr;  // = adr_sr + adr_offset

reg stb_l;      // "local" stb signal (to distinguish from stb_o)
reg we_l;       // "local" we  signal (to distinguish from we_o)

reg [`NIBBLE_SIZE*ADR_DIGITS_PP-1:0] rd_adr_sr; // sr for printing addresses
reg [`NIBBLE_SIZE*ADR_DIGITS_PP-1:0] adr_sr;    // "nibble" shift register
reg [`NIBBLE_SIZE*DAT_DIGITS_PP-1:0] dat_sr;    // "nibble" shift register
reg [`NIBBLE_SIZE*QTY_DIGITS_PP-1:0] qty_sr;    // "nibble" shift register
reg [1:0] command;
reg [`NIBBLE_SIZE*QTY_DIGITS_PP-1:0] adr_offset;   // counts from 0 to qty_sr
reg reset_adr_offset;
reg incr_adr_offset;

    // For the command buffer
reg [CMD_PTR_BITS_PP-1:0] cmd_ptr; // Offset from start of command.
reg reset_cmd_ptr;        // High == set command pointer to zero.
reg incr_cmd_ptr;         // Used for "write port" side of the command buffer
reg decr_cmd_ptr;         // Used for "write port" side of the command buffer
reg cmd_buffer_write;
reg [7:0] cmd_buffer [0:CMD_BUFFER_SIZE_PP-1];
wire [7:0] cmd_char;
wire [7:0] lc_cmd_char;   // Lowercase version of cmd_char

    // For the state machine
reg [4:0] m1_state;
reg [4:0] m1_next_state;

    // For various counters
reg reset_rd_field_count;
reg reset_rd_digit_count;
reg incr_rd_field_count;
reg incr_rd_digit_count;
reg [RD_FIELD_COUNT_BITS_PP-1:0] rd_field_count;  // "fields displayed"
reg [RD_DIGIT_COUNT_BITS_PP-1:0] rd_digit_count;  // "digits displayed"
reg [WATCHDOG_TIMER_BITS_PP-1:0] watchdog_timer_count;
reg reset_watchdog;

     // For the rs232 interface
wire [2:0] rs232_rx_error;
wire rs232_tx_load;
wire rs232_tx_load_request;
wire rs232_rx_data_ready;
wire [7:0] rs232_rx_char;
wire [7:0] rs232_tx_char;   // Either rs232_rx_char or msg_char

//--------------------------------------------------------------------------
// Instantiations
//--------------------------------------------------------------------------


// These defines are for the rs232 interface
`define START_BITS 1
`define DATA_BITS 8
`define STOP_BITS 1
//`define CLOCK_FACTOR 16
`define CLOCK_FACTOR 8   // for use with divided clock

// This unit generates the correct 16x transmit clock (enable) frequency
// which is used for the serial transmit operation.
clock_gen_select clock_unit
  (
   .clk(clk_i),
   .reset(reset_i),
   .rate_select(3'b100),         // 115,200 baud
   .clk_out(serial_clk_16x)
  );

// A transmitter, which asserts load_request at the end of the currently
// transmitted word.  The tx_clk must be a "clock enable" (narrow positive
// pulse) which occurs at 16x the desired transmit rate.  If load_request
// is connected directly to load, the unit will transmit continuously.
rs232tx #(
          `START_BITS,   // start_bits
          `DATA_BITS,    // data_bits
          `STOP_BITS,    // stop_bits (add intercharacter delay...)
          `CLOCK_FACTOR  // clock_factor
         )
         rs232_tx_block // instance name
         ( 
          .clk(clk_i),
          .tx_clk(serial_clk_16x),
          .reset(reset_i),
          .load(rs232_tx_load),
          .data(rs232_tx_char),
          .load_request(rs232_tx_load_request),
          .txd(rs232_txd_o)
         );

// A receiver, which asserts "word_ready" to indicate a received word.
// Asserting "read_word" will cause "word_ready" to go low again if it was high.
// The character is held in the output register, during the time the next
//   character is coming in.
rs232rx #(
          `START_BITS,  // start_bits