//-----------------------------------------------------------------------------
//
// Author: John Clayton
// Date  : Nov.   5, 2001
// Update: Nov.   5, 2001 Obtained this file from "build_9b" project.
// Update: Nov.  30, 2001 First physical synthesis. (only "store" implemented)
// Update: Dec.  14, 2001 "Loads" and "stores" implemented.  Still debugging.
// Update: Dec.  18, 2001 Finished debugging.  "memory_sizer_dual_path" works
//                        at 25 MHz, requires 300 slices.  "memory_sizer"
//                        requires only 200 slices, but operates slower.
//                        (tested at 12.5 MHz only.  It worked fine.)
//
// Description
//-----------------------------------------------------------------------------
// This targets an XC2S200 board which was created for educational purposes.
//
// There are:
//    8  LEDs (led[7:0])
//    4  switches (switch[3:0])
//    1  clock of 32.000 MHz clock, present on GCLK1
//    1  clock of 49.152 MHz clock, present on GCLK0
//    4  lines of ps2 clock input (port A in documentation notes)
//    4  lines of ps2 data input (port A in documentation notes)
//    16 lines of LCD panel control (port B in documentation notes)
//    2  lines of rs232 serial connection (port C in documentation notes)
//-----------------------------------------------------------------------------

// NOTE: This build is for testing out a "memory_sizer" block.
//       The memory_sizer block allows a microprocessor to generate different
//       types of memory accesses (8-bit, 16-bit, 32-bit etc.) to different
//       and various sizes of memory.  It handles the "byte steering" and
//       multiple cycle action needed in order to accomplish these accesses
//       for the microprocessor.  In this build, the rs232_syscon acts as the
//       microprocessor (stand alone).
//
//       The dual-ported RAMs exhibit "little endian" transformation.
//
//       That is:  Sequential bytes, 00, 01, 02, 03 on the s8 side emerge
//                 on the s16 side:  01000302.
//                 on the s32 side:  03020100.
//
//                 Sequential words, 0100, 0302 on the s16 side emerge
//                 on the s32 side:  03020100.
//
//       This is called "little endian".  It can be quite confusing at times!

// The following 'include line must be used with Synplify to create EDIF
// The line must be commented for ModelSim.
//`include "d:\synplicity\synplify_70\lib\xilinx\virtex.v"

module top (
//  dat_o,
//  debug_o,
  sys_clk_0,
  sys_clk_1,
  switch,
  led,
  ps2_clk,
  ps2_data,
  lcd_drive,
  rs232_rxd,
  rs232_txd
  );
  
//output [15:0] dat_o;      // for debug only
//output [13:0] debug_o;    // for debug only

// I/O declarations
input sys_clk_0;      // 49.152 MHz
input sys_clk_1;      // 32.000 MHz
input [3:0] switch;
input rs232_rxd;

inout [3:0] ps2_clk;
inout [3:0] ps2_data;

output [7:0] led;

output [15:0] lcd_drive;
output rs232_txd;

// Internal signal declarations

wire [7:0] r0_wire;  // "Read" regs.  Used to "hold" pin locations, so that
wire [4:0] r1_wire;  // the synthesis tools do not complain about these pins
                     // being present in the constraints file and not in the
                     // design...

     // Clock signals
wire clk_s0;            // 49.152/2 MHz = 24.576 MHz
wire clk_s1;            // 32.000/2 MHz = 16.000 MHz
reg  [1:0] clk_count0;  // Counter used to generate clock
reg  [1:0] clk_count1;  // Counter used to generate clock

     // Signals from risc processor
wire [15:0] risc_aux_adr;     // AUX (expansion) bus
wire        risc_aux_we;      // AUX we
wire [15:0] risc_prog_dat;    // Program data
wire [12:0] risc_prog_adr;    // (Up to 8k words possible)
wire [8:0]  risc_ram_adr;     // RAM file address
wire [7:0]  risc_ram_dat_o;   // RAM file data
wire [7:0]  risc_ram_dat_i;   // RAM file data
wire        risc_ram_we;      // RAM we
wire        risc_stb;         // Clock enable for risc processor

     // Signals from rs232_syscon
wire [15:0] adr;        // A side address
wire [7:0] dat;         // A side data
wire we;
wire stb;
wire rst;
wire master_br;


    // Address decode signals
wire       code_space;  // High for access to code space (AUX bus)
wire       rgb_space;   // High for access to rgb space (AUX bus)
wire       io_space;    // High for access to I/O space (AUX bus)
wire [1:0] io_sel;      // 1 of 4 is active high for I/O space accesses

    // Hardware breakpoint and single stepping signals
wire [12:0] break_prog_adr;  // For hardware breakpoint on prog. adr
wire [13:0] break_prog_dat;  // For hardware breakpoint on prog. dat
wire [ 1:0] break_enable;    // bit 1: enables dat BP, bit 0: enables adr BP
wire        breakpoint;      // 1 = any breakpoint condition encountered.
reg  [ 5:0] step_count;      // Number of steps remaining to execute
wire [ 5:0] clocks_to_step;  // Desired number of steps to execute
wire        begin_stepping;       // Automatically resets itself when written!
wire        stepping_active;      // 1 during single stepping
wire        reset_single_stepper; // 1 during breakpoint or reset
wire [ 1:0] processor_control; // Contains two signals (renamed below)
wire        run_free;          // Allows processor to run constantly
wire        forced_reset;      // Forces the processor into reset
wire        bus_rdy;           // 1 = processor can execute this clock cycle.


    // A side RAM signals
wire [7:0] code_ram_dat_o;
wire [2:0] rgb_ram_dat_o;
wire [7:0] regfile_ram_dat_o;

    // B side (Peripheral side) RAM signals
wire [2:0]  pixel_dat;
wire [13:0] pixel_adr;   // (12288 pixels addressed)

    // Other...
wire reset = switch[0];  // Simply a renaming exercise

wire [1:0] risc_debug;

//--------------------------------------------------------------------------
// Clock generation
//--------------------------------------------------------------------------

// This uses up an additional GCLK resource.
always @(posedge sys_clk_0)
begin
  clk_count0 <= clk_count0 + 1;
end
assign clk_s0 = clk_count0[0];

// This uses up an additional GCLK resource.
always @(posedge sys_clk_1)
begin
  clk_count1 <= clk_count1 + 1;
end
assign clk_s1 = clk_count1[0];


//--------------------------------------------------------------------------
// Debug Code
//--------------------------------------------------------------------------
//assign dat_o[15:0] = {risc_ram_adr[7:0],risc_ram_dat_o};
//assign debug_o[7:0] = risc_prog_adr[7:0];
//assign debug_o[13] = risc_stb;
//assign debug_o[9] = risc_ram_we;
//assign debug_o[10] = risc_aux_we;
//assign debug_o[8] = rst;
//assign debug_o[12:11] = {risc_prog_adr[9:8]};

//--------------------------------------------------------------------------
// Instantiations
//--------------------------------------------------------------------------

vga_128_by_92 lcd_block (
  .lcd_clk(sys_clk_0),
  .lcd_reset(switch[3]),
  .pixel_dat_i(pixel_dat),
  .pixel_adr_o(pixel_adr),
  .lcd_drive(lcd_drive)
  );

assign risc_stb = (bus_rdy || rst);
risc16f84_clk2x 
  processor1
  (
   .prog_dat_i(risc_prog_dat[13:0]),  // [13:0] ROM read data
   .prog_adr_o(risc_prog_adr),        // [12:0] ROM address
   .ram_dat_i(risc_ram_dat_i),        // [7:0] RAM read data
   .ram_dat_o(risc_ram_dat_o),        // [7:0] RAM write data
   .ram_adr_o(risc_ram_adr),          // [8:0] RAM address
   .ram_we_o(risc_ram_we),            // RAM write strobe (H active)
   .aux_adr_o(risc_aux_adr),    // [15:0] Auxiliary address bus
   .aux_dat_io(dat),            // [7:0] AUX data (shared w/rs232_syscon)
   .aux_we_o(risc_aux_we),      // Auxiliary write strobe (H active)
   .int0_i(1'b0),               // PORT-B(0) INT
   .reset_i(rst),         // Power-on reset (H active)
   .clk_en_i(risc_stb),   // Clock enable for all clocked logic
   .clk_i(clk_s0)      // Clock input
   );


rs232_syscon #(
               4,             // Number of Hex digits for addresses.
               2,             // Number of Hex digits for data.
               2,             // Number of Hex digits for quantity.
               16,            // Characters in the input buffer
               4,             // Bits in the buffer pointer
               63,            // Clocks before watchdog timer expires
               6,             // Bits in watchdog timer
               8,             // Number of data fields displayed per line