////////////////////////////////////////////////////////////////////// ////                                                              ////////  eth_ocm.v                                                   ////////                                                              ////////  This file is part of the Ethernet IP core project           ////////  http://www.opencores.org/projects/ethmac/                   ////////                                                              ////////  Author(s):                                                  ////////      - Igor Mohor (igorM@opencores.org)                      ////////      - Jakob Jones (jrjonsie@gmail.com)                      ////                    ////                                                              ////////  *NOTE* This file has been modified from its original        ////////  version. The file was renamed from eth_top.v to eth_ocm.v   ////////  The file has been modified to work more efficiently with    ////////  with Altera's Avalon BUS. The original wishbone interface   ////////  has been removed and replaced with an eth_avalon module.    ////////                                                              ////////  All additional information is available in the Readme.txt   ////////  file.                                                       ////////                                                              //////////////////////////////////////////////////////////////////////////////                                                              //////// Copyright (C) 2001, 2002 Authors                             ////////                                                              //////// This source file may be used and distributed without         //////// restriction provided that this copyright statement is not    //////// removed from the file and that any derivative work contains  //////// the original copyright notice and the associated disclaimer. ////////                                                              //////// This source file is free software; you can redistribute it   //////// and/or modify it under the terms of the GNU Lesser General   //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any   //////// later version.                                               ////////                                                              //////// This source is distributed in the hope that it will be       //////// useful, but WITHOUT ANY WARRANTY; without even the implied   //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //////// PURPOSE.  See the GNU Lesser General Public License for more //////// details.                                                     ////////                                                              //////// You should have received a copy of the GNU Lesser General    //////// Public License along with this source; if not, download it   //////// from http://www.opencores.org/lgpl.shtml                     ////////                                                              ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: eth_ocm.v,v $// Revision 1.52  2005/03/21 20:07:18  igorm// Some small fixes + some troubles fixed.//// Revision 1.51  2005/02/21 11:13:17  igorm// Defer indication fixed.//// Revision 1.50  2004/04/26 15:26:23  igorm// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the//   previous update of the core.// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER//   register. (thanks to Mathias and Torbjorn)// - Multicast reception was fixed. Thanks to Ulrich Gries//// Revision 1.49  2003/11/12 18:24:59  tadejm// WISHBONE slave changed and tested from only 32-bit accesss to byte access.//// Revision 1.48  2003/10/17 07:46:16  markom// mbist signals updated according to newest convention//// Revision 1.47  2003/10/06 15:43:45  knguyen// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).//// Revision 1.46  2003/01/30 13:30:22  tadejm// Defer indication changed.//// Revision 1.45  2003/01/22 13:49:26  tadejm// When control packets were received, they were ignored in some cases.//// Revision 1.44  2003/01/21 12:09:40  mohor// When receiving normal data frame and RxFlow control was switched on, RXB// interrupt was not set.//// Revision 1.43  2002/11/22 01:57:06  mohor// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort// synchronized.//// Revision 1.42  2002/11/21 00:09:19  mohor// TPauseRq synchronized to tx_clk.//// Revision 1.41  2002/11/19 18:13:49  mohor// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.//// Revision 1.40  2002/11/19 17:34:25  mohor// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying// that a frame was received because of the promiscous mode.//// Revision 1.39  2002/11/18 17:31:55  mohor// wb_rst_i is used for MIIM reset.//// Revision 1.38  2002/11/14 18:37:20  mohor// r_Rst signal does not reset any module any more and is removed from the design.//// Revision 1.37  2002/11/13 22:25:36  tadejm// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.//// Revision 1.36  2002/10/18 17:04:20  tadejm// Changed BIST scan signals.//// Revision 1.35  2002/10/11 13:36:58  mohor// Typo error fixed. (When using Bist)//// Revision 1.34  2002/10/10 16:49:50  mohor// Signals for WISHBONE B3 compliant interface added.//// Revision 1.33  2002/10/10 16:29:30  mohor// BIST added.//// Revision 1.32  2002/09/20 17:12:58  mohor// CsMiss added. When address between 0x800 and 0xfff is accessed within// Ethernet Core, error acknowledge is generated.//// Revision 1.31  2002/09/12 14:50:17  mohor// CarrierSenseLost bug fixed when operating in full duplex mode.//// Revision 1.30  2002/09/10 10:35:23  mohor// Ethernet debug registers removed.//// Revision 1.29  2002/09/09 13:03:13  mohor// Error acknowledge is generated when accessing BDs and RST bit in the// MODER register (r_Rst) is set.//// Revision 1.28  2002/09/04 18:44:10  mohor// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4// connected.//// Revision 1.27  2002/07/25 18:15:37  mohor// RxAbort changed. Packets received with MRxErr (from PHY) are also// aborted.//// Revision 1.26  2002/07/17 18:51:50  mohor// EXTERNAL_DMA removed. External DMA not supported.//// Revision 1.25  2002/05/03 10:15:50  mohor// Outputs registered. Reset changed for eth_wishbone module.//// Revision 1.24  2002/04/22 14:15:42  mohor// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is// selected in eth_defines.v//// Revision 1.23  2002/03/25 13:33:53  mohor// md_padoen_o changed to md_padoe_o. Signal was always active high, just// name was incorrect.//// Revision 1.22  2002/02/26 16:59:54  mohor// Small fixes for external/internal DMA missmatches.//// Revision 1.21  2002/02/26 16:21:00  mohor// Interrupts changed in the top file//// Revision 1.20  2002/02/18 10:40:17  mohor// Small fixes.//// Revision 1.19  2002/02/16 14:03:44  mohor// Registered trimmed. Unused registers removed.//// Revision 1.18  2002/02/16 13:06:33  mohor// EXTERNAL_DMA used instead of WISHBONE_DMA.//// Revision 1.17  2002/02/16 07:15:27  mohor// Testbench fixed, code simplified, unused signals removed.//// Revision 1.16  2002/02/15 13:49:39  mohor// RxAbort is connected differently.//// Revision 1.15  2002/02/15 11:38:26  mohor// Changes that were lost when updating from 1.11 to 1.14 fixed.//// Revision 1.14  2002/02/14 20:19:11  billditt// Modified for Address Checking,// addition of eth_addrcheck.v//// Revision 1.13  2002/02/12 17:03:03  mohor// HASH0 and HASH1 registers added. Registers address width was// changed to 8 bits.//// Revision 1.12  2002/02/11 09:18:22  mohor// Tx status is written back to the BD.//// Revision 1.11  2002/02/08 16:21:54  mohor// Rx status is written back to the BD.//// Revision 1.10  2002/02/06 14:10:21  mohor// non-DMA host interface added. Select the right configutation in eth_defines.//// Revision 1.9  2002/01/23 10:28:16  mohor// Link in the header changed.//// Revision 1.8  2001/12/05 15:00:16  mohor// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors// instead of the number of RX descriptors).//// Revision 1.7  2001/12/05 10:45:59  mohor// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.//// Revision 1.6  2001/10/19 11:24:29  mohor// Number of addresses (wb_adr_i) minimized.//// Revision 1.5  2001/10/19 08:43:51  mohor// eth_timescale.v changed to timescale.v This is done because of the// simulation of the few cores in a one joined project.//// Revision 1.4  2001/10/18 12:07:11  mohor// Status signals changed, Adress decoding changed, interrupt controller// added.//// Revision 1.3  2001/09/24 15:02:56  mohor// Defines changed (All precede with ETH_). Small changes because some// tools generate warnings when two operands are together. Synchronization// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC// demands).//// Revision 1.2  2001/08/15 14:03:59  mohor// Signal names changed on the top level for easier pad insertion (ASIC).//// Revision 1.1  2001/08/06 14:44:29  mohor// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).// Include files fixed to contain no path.// File names and module names changed ta have a eth_ prologue in the name.// File eth_timescale.v is used to define timescale// All pin names on the top module are changed to contain _I, _O or _OE at the end.// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O// and Mdo_OE. The bidirectional signal must be created on the top level. This// is done due to the ASIC tools.//// Revision 1.2  2001/08/02 09:25:31  mohor// Unconnected signals are now connected.//// Revision 1.1  2001/07/30 21:23:42  mohor// Directory structure changed. Files checked and joind together.//////// `include "eth_defines.v"`include "timescale.v"module eth_ocm #(   parameter   TOTAL_DESCRIPTORS=128,                    parameter   TX_FIFO_SIZE_IN_BYTES=128,                    parameter   RX_FIFO_SIZE_IN_BYTES=4096  ) (    //Avalon common    input               av_clk,    input               av_reset,    //Avalon control port    input   [9:0]       av_address,    input               av_chipselect,    input               av_write,    input               av_read,    input   [31:0]      av_writedata,    output  [31:0]      av_readdata,    output              av_waitrequest_n,    //Avalon TX memory port    input   [31:0]      av_tx_readdata,    input               av_tx_waitrequest,    input               av_tx_readdatavalid,    output  [31:0]      av_tx_address,    output              av_tx_read,    //Avalon RX memory port    input               av_rx_waitrequest,    output  [31:0]      av_rx_address,    output              av_rx_write,    output  [31:0]      av_rx_writedata,    output  [3:0]       av_rx_byteenable,    //MII TX    input               mtx_clk_pad_i,    output  [3:0]       mtxd_pad_o,    output              mtxen_pad_o,    output              mtxerr_pad_o,    //MII RX    input               mrx_clk_pad_i,    input   [3:0]       mrxd_pad_i,    input               mrxdv_pad_i,    input               mrxerr_pad_i,    input               mcoll_pad_i,    input               mcrs_pad_i,     //MII Management    output              mdc_pad_o,    input               md_pad_i,    output              md_pad_o,    output              md_padoe_o,        //Avalon interrupt    output              av_irq    // Bist`ifdef ETH_BIST    ,    // debug chain signals    input               mbist_si_i,       // bist scan serial in    input               mbist_so_o,       // bist scan serial out    input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i      // bist chain shift control`endif);localparam  Tp = 1;             // Delay for simulationswire     [7:0]  r_ClkDiv;wire            r_MiiNoPre;wire    [15:0]  r_CtrlData;