wire     [4:0]  r_FIAD;wire     [4:0]  r_RGAD;wire            r_WCtrlData;wire            r_RStat;wire            r_ScanStat;wire            NValid_stat;wire            Busy_stat;wire            LinkFail;wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)wire            WCtrlDataStart;wire            RStatStart;wire            UpdateMIIRX_DATAReg;wire            TxStartFrm;wire            TxEndFrm;wire            TxUsedData;wire     [7:0]  TxData;wire            TxRetry;wire            TxAbort;wire            TxUnderRun;wire            TxDone;reg             WillSendControlFrame_sync1;reg             WillSendControlFrame_sync2;reg             WillSendControlFrame_sync3;reg             RstTxPauseRq;reg             TxPauseRq_sync1;reg             TxPauseRq_sync2;reg             TxPauseRq_sync3;reg             TPauseRq;// Connecting Miim moduleeth_miim miim1(  .Clk(av_clk),                           .Reset(av_reset),                   .Divider(r_ClkDiv),   .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),   .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),   .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),   .MdoEn(md_padoe_o),                     .Mdc(mdc_pad_o),                    .Busy(Busy_stat),   .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),   .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg));wire        av_cs;wire        RegCs;          // Connected to registerswire [31:0] RegDataOut;     // Multiplexed to av_readdatawire        r_RecSmall;     // Receive small frameswire        r_LoopBck;      // Loopbackwire        r_TxEn;         // Tx Enablewire        r_RxEn;         // Rx Enablewire        MRxDV_Lb;       // Muxed MII receive data validwire        MRxErr_Lb;      // Muxed MII Receive Errorwire  [3:0] MRxD_Lb;        // Muxed MII Receive Datawire        Transmitting;   // Indication that TxEthMAC is transmittingwire        r_HugEn;        // Huge packet enablewire        r_DlyCrcEn;     // Delayed CRC enabledwire [15:0] r_MaxFL;        // Maximum frame lengthwire [15:0] r_MinFL;        // Minimum frame lengthwire        ShortFrame;wire        DribbleNibble;  // Extra nibble receivedwire        ReceivedPacketTooBig; // Received packet is too bigwire [47:0] r_MAC;          // MAC addresswire        LoadRxStatus;   // Rx status was loadedwire [31:0] r_HASH0;        // HASH table, lower 4 byteswire [31:0] r_HASH1;        // HASH table, upper 4 byteswire  [7:0] r_TxBDNum;      // Receive buffer descriptor numberwire  [6:0] r_IPGT;         // wire  [6:0] r_IPGR1;        // wire  [6:0] r_IPGR2;        // wire  [5:0] r_CollValid;    // wire [15:0] r_TxPauseTV;    // Transmit PAUSE valuewire        r_TxPauseRq;    // Transmit PAUSE requestwire  [3:0] r_MaxRet;       //wire        r_NoBckof;      // wire        r_ExDfrEn;      // wire        r_TxFlow;       // Tx flow control enablewire        r_IFG;          // Minimum interframe gap for incoming packetswire        TxB_IRQ;        // Interrupt Tx Bufferwire        TxE_IRQ;        // Interrupt Tx Errorwire        RxB_IRQ;        // Interrupt Rx Bufferwire        RxE_IRQ;        // Interrupt Rx Errorwire        Busy_IRQ;       // Interrupt Busy (lack of buffers)wire        BDAck;wire [31:0] BD_av_readdata; // av_readdata that comes from the avalon module (for buffer descriptors read/write)wire        BDCs;           // Buffer descriptor CSwire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set                            // but data is not valid.wire        r_Pad;wire        r_CrcEn;wire        r_FullD;wire        r_Pro;wire        r_Bro;wire        r_NoPre;wire        r_RxFlow;wire        r_PassAll;wire        TxCtrlEndFrm;wire        StartTxDone;wire        SetPauseTimer;wire        TxUsedDataIn;wire        TxDoneIn;wire        TxAbortIn;wire        PerPacketPad;wire        PadOut;wire        PerPacketCrcEn;wire        CrcEnOut;wire        TxStartFrmOut;wire        TxEndFrmOut;wire        ReceivedPauseFrm;wire        ControlFrmAddressOK;wire        RxStatusWriteLatched_sync2;wire        LateCollision;wire        DeferIndication;wire        LateCollLatched;wire        DeferLatched;wire        RstDeferLatched;wire        CarrierSenseLost;wire        temp_av_waitrequest_n;wire [31:0] temp_av_readdata;`ifdef ETH_REGISTERED_OUTPUTS  reg         temp_av_waitrequest_n_reg;  reg [31:0]  temp_av_readdata_reg;`endifassign av_cs            = av_chipselect & (av_write | av_read);assign RegCs            = av_cs & ~av_address[9] & ~av_address[8];  // 0x0   - 0x0FFassign BDCs             = av_cs & ~av_address[9] &  av_address[8];  // 0x100 - 0x1FFassign CsMiss           = av_cs &  av_address[9];                   // 0x200 - 0x3FFassign temp_av_readdata = RegCs? RegDataOut : BD_av_readdata;assign temp_av_waitrequest_n = RegCs | BDAck | CsMiss;`ifdef ETH_REGISTERED_OUTPUTS  assign av_waitrequest_n   = temp_av_waitrequest_n_reg;  assign av_readdata        = temp_av_readdata_reg;`else  assign av_waitrequest_n   = temp_av_waitrequest_n;  assign av_readdata        = temp_av_readdata;`endif`ifdef ETH_REGISTERED_OUTPUTS  always @ (posedge av_clk or posedge av_reset)  begin    if(av_reset) begin        temp_av_waitrequest_n_reg   <=#Tp 1'b0;        temp_av_readdata_reg        <=#Tp 32'h0;    end else begin        temp_av_waitrequest_n_reg   <=#Tp temp_av_waitrequest_n & ~temp_av_waitrequest_n_reg;        temp_av_readdata_reg        <=#Tp temp_av_readdata;      end  end`endif// Connecting Ethernet registerseth_registers ethreg1(  .DataIn(av_writedata),                  .Address(av_address[7:0]),                  .Rw(av_write & ~av_read),   .Cs(RegCs),                             .Clk(av_clk),                               .Reset(av_reset),   .DataOut(RegDataOut),                   .r_RecSmall(r_RecSmall),   .r_Pad(r_Pad),                          .r_HugEn(r_HugEn),                          .r_CrcEn(r_CrcEn),   .r_DlyCrcEn(r_DlyCrcEn),                .r_FullD(r_FullD),   .r_ExDfrEn(r_ExDfrEn),                  .r_NoBckof(r_NoBckof),                      .r_LoopBck(r_LoopBck),   .r_IFG(r_IFG),                          .r_Pro(r_Pro),                              .r_Iam(),   .r_Bro(r_Bro),                          .r_NoPre(r_NoPre),                          .r_TxEn(r_TxEn),   .r_RxEn(r_RxEn),                        .Busy_IRQ(Busy_IRQ),                        .RxE_IRQ(RxE_IRQ),   .RxB_IRQ(RxB_IRQ),                      .TxE_IRQ(TxE_IRQ),                          .TxB_IRQ(TxB_IRQ),   .r_IPGT(r_IPGT),   .r_IPGR1(r_IPGR1),                      .r_IPGR2(r_IPGR2),                          .r_MinFL(r_MinFL),   .r_MaxFL(r_MaxFL),                      .r_MaxRet(r_MaxRet),                        .r_CollValid(r_CollValid),   .r_TxFlow(r_TxFlow),                    .r_RxFlow(r_RxFlow),                        .r_PassAll(r_PassAll),   .r_MiiNoPre(r_MiiNoPre),                .r_ClkDiv(r_ClkDiv),   .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),   .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),   .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),                     .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),   .r_TxBDNum(r_TxBDNum),                  .int_o(av_irq),  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),   .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),   .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),   .SetPauseTimer(SetPauseTimer)  );wire  [7:0] RxData;wire        RxValid;wire        RxStartFrm;wire        RxEndFrm;wire        RxAbort;wire        WillTransmit;            // Will transmit (to RxEthMAC)wire        ResetCollision;          // Reset Collision (for synchronizing collision)wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)wire        WillSendControlFrame;wire        ReceiveEnd;wire        ReceivedPacketGood;wire        ReceivedLengthOK;wire        InvalidSymbol;wire        LatchedCrcError;wire        RxLateCollision;wire  [3:0] RetryCntLatched;   wire  [3:0] RetryCnt;   wire        StartTxAbort;   wire        MaxCollisionOccured;   wire        RetryLimit;   wire        StatePreamble;   wire  [1:0] StateData; // Connecting MACControleth_maccontrol maccontrol1(  .MTxClk(mtx_clk_pad_i),                       .TPauseRq(TPauseRq),   .TxPauseTV(r_TxPauseTV),                      .TxDataIn(TxData),   .TxStartFrmIn(TxStartFrm),                    .TxEndFrmIn(TxEndFrm),   .TxUsedDataIn(TxUsedDataIn),                  .TxDoneIn(TxDoneIn),   .TxAbortIn(TxAbortIn),                        .MRxClk(mrx_clk_pad_i),   .RxData(RxData),                              .RxValid(RxValid),   .RxStartFrm(RxStartFrm),                      .RxEndFrm(RxEndFrm),  .ReceiveEnd(ReceiveEnd),                      .ReceivedPacketGood(ReceivedPacketGood),  .TxFlow(r_TxFlow),   .RxFlow(r_RxFlow),                            .DlyCrcEn(r_DlyCrcEn),  .MAC(r_MAC),                                  .PadIn(r_Pad | PerPacketPad),   .PadOut(PadOut),                              .CrcEnIn(r_CrcEn | PerPacketCrcEn),   .CrcEnOut(CrcEnOut),                          .TxReset(av_reset),   .RxReset(av_reset),                           .ReceivedLengthOK(ReceivedLengthOK),  .TxDataOut(TxDataOut),                        .TxStartFrmOut(TxStartFrmOut),   .TxEndFrmOut(TxEndFrmOut),                    .TxUsedDataOut(TxUsedData),   .TxDoneOut(TxDone),                           .TxAbortOut(TxAbort),   .WillSendControlFrame(WillSendControlFrame),  .TxCtrlEndFrm(TxCtrlEndFrm),   .ReceivedPauseFrm(ReceivedPauseFrm),          .ControlFrmAddressOK(ControlFrmAddressOK),  .SetPauseTimer(SetPauseTimer),  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),                .r_PassAll(r_PassAll));wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)wire Collision;               // Synchronized Collisionreg CarrierSense_Tx1;reg CarrierSense_Tx2;reg Collision_Tx1;reg Collision_Tx2;reg RxEnSync;                 // Synchronized Receive Enablereg WillTransmit_q;reg WillTransmit_q2;// Muxed MII receive data validassign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;// Muxed MII Receive Errorassign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;// Muxed MII Receive Dataassign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];// Connecting TxEthMACeth_txethmac txethmac1(  .MTxClk(mtx_clk_pad_i),             .Reset(av_reset),                   .CarrierSense(TxCarrierSense),   .Collision(Collision),              .TxData(TxDataOut),                 .TxStartFrm(TxStartFrmOut),   .TxUnderRun(TxUnderRun),            .TxEndFrm(TxEndFrmOut),             .Pad(PadOut),    .MinFL(r_MinFL),                    .CrcEn(CrcEnOut),                   .FullD(r_FullD),   .HugEn(r_HugEn),                    .DlyCrcEn(r_DlyCrcEn),              .IPGT(r_IPGT),   .IPGR1(r_IPGR1),                    .IPGR2(r_IPGR2),                    .CollValid(r_CollValid),   .MaxRet(r_MaxRet),                  .NoBckof(r_NoBckof),                .ExDfrEn(r_ExDfrEn),   .MaxFL(r_MaxFL),                    .MTxEn(mtxen_pad_o),                .MTxD(mtxd_pad_o),   .MTxErr(mtxerr_pad_o),              .TxUsedData(TxUsedDataIn),          .TxDone(TxDoneIn),   .TxRetry(TxRetry),                  .TxAbort(TxAbortIn),                .WillTransmit(WillTransmit),   .ResetCollision(ResetCollision),    .RetryCnt(RetryCnt),                .StartTxDone(StartTxDone),   .StartTxAbort(StartTxAbort),        .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),     .DeferIndication(DeferIndication),  .StatePreamble(StatePreamble),      .StateData(StateData)   );wire  [15:0]  RxByteCnt;wire          RxByteCntEq0;wire          RxByteCntGreat2;wire          RxByteCntMaxFrame;wire          RxCrcError;wire          RxStateIdle;wire          RxStatePreamble;wire          RxStateSFD;wire   [1:0]  RxStateData;wire          AddressMiss;// Connecting RxEthMACeth_rxethmac rxethmac1(  .MRxClk(mrx_clk_pad_i),               .MRxDV(MRxDV_Lb),                     .MRxD(MRxD_Lb),  .Transmitting(Transmitting),          .HugEn(r_HugEn),                      .DlyCrcEn(r_DlyCrcEn),   .MaxFL(r_MaxFL),                      .r_IFG(r_IFG),                        .Reset(av_reset),