# TCL File Generated by Component Editor 8.0sp1# Wed Oct 08 08:58:57 MDT 2008# DO NOT MODIFY# +-----------------------------------# | # | eth_ocm "OpenCores 10/100 Ethernet MAC Avalon" v8.0.2# | Jakob Jones 2008.10.08.08:58:57# | # | # | C:/altera/80/ip/sopc_builder_ip/eth_ocm/eth_ocm.v# | # |    ./eth_ocm.v syn, sim# | # +-----------------------------------# +-----------------------------------# | module eth_ocm# | set_module_property DESCRIPTION ""set_module_property NAME eth_ocmset_module_property VERSION 8.0.2set_module_property GROUP "Interface Protocols/Ethernet"set_module_property AUTHOR "Jakob Jones"set_module_property DISPLAY_NAME "OpenCores 10/100 Ethernet MAC Avalon"set_module_property TOP_LEVEL_HDL_FILE eth_ocm.vset_module_property TOP_LEVEL_HDL_MODULE eth_ocmset_module_property INSTANTIATE_IN_SYSTEM_MODULE trueset_module_property EDITABLE falseset_module_property SIMULATION_MODEL_IN_VERILOG falseset_module_property SIMULATION_MODEL_IN_VHDL falseset_module_property SIMULATION_MODEL_HAS_TULIPS falseset_module_property SIMULATION_MODEL_IS_OBFUSCATED false# | # +-----------------------------------# +-----------------------------------# | files# | add_file eth_ocm.v {SYNTHESIS SIMULATION}# | # +-----------------------------------# +-----------------------------------# | parameters# | add_parameter TOTAL_DESCRIPTORS int 128 "Total number of DMA descriptors"set_parameter_property TOTAL_DESCRIPTORS DISPLAY_NAME TOTAL_DESCRIPTORSset_parameter_property TOTAL_DESCRIPTORS UNITS Noneset_parameter_property TOTAL_DESCRIPTORS AFFECTS_PORT_WIDTHS trueadd_parameter TX_FIFO_SIZE_IN_BYTES int 128 "Transmit FIFO size in bytes"set_parameter_property TX_FIFO_SIZE_IN_BYTES DISPLAY_NAME TX_FIFO_SIZE_IN_BYTESset_parameter_property TX_FIFO_SIZE_IN_BYTES UNITS Noneset_parameter_property TX_FIFO_SIZE_IN_BYTES AFFECTS_PORT_WIDTHS trueadd_parameter RX_FIFO_SIZE_IN_BYTES int 4096 "Receive FIFO size in bytes"set_parameter_property RX_FIFO_SIZE_IN_BYTES DISPLAY_NAME RX_FIFO_SIZE_IN_BYTESset_parameter_property RX_FIFO_SIZE_IN_BYTES UNITS Noneset_parameter_property RX_FIFO_SIZE_IN_BYTES AFFECTS_PORT_WIDTHS true# | # +-----------------------------------# +-----------------------------------# | connection point control_port# | add_interface control_port avalon endset_interface_property control_port holdTime 0set_interface_property control_port linewrapBursts falseset_interface_property control_port minimumUninterruptedRunLength 1set_interface_property control_port bridgesToMaster ""set_interface_property control_port isMemoryDevice falseset_interface_property control_port burstOnBurstBoundariesOnly falseset_interface_property control_port addressSpan 4096set_interface_property control_port timingUnits Cyclesset_interface_property control_port setupTime 0set_interface_property control_port writeWaitTime 0set_interface_property control_port isNonVolatileStorage falseset_interface_property control_port addressAlignment DYNAMICset_interface_property control_port maximumPendingReadTransactions 0set_interface_property control_port readWaitTime 1set_interface_property control_port readLatency 0set_interface_property control_port printableDevice falseset_interface_property control_port ASSOCIATED_CLOCK clockadd_interface_port control_port av_address address Input 10add_interface_port control_port av_chipselect chipselect Input 1add_interface_port control_port av_write write Input 1add_interface_port control_port av_read read Input 1add_interface_port control_port av_writedata writedata Input 32add_interface_port control_port av_readdata readdata Output 32add_interface_port control_port av_waitrequest_n waitrequest_n Output 1# | # +-----------------------------------# +-----------------------------------# | connection point clock# | add_interface clock clock endset_interface_property clock ptfSchematicName ""add_interface_port clock av_clk clk Input 1add_interface_port clock av_reset reset Input 1# | # +-----------------------------------# +-----------------------------------# | connection point tx_master# | add_interface tx_master avalon startset_interface_property tx_master linewrapBursts falseset_interface_property tx_master adaptsTo ""set_interface_property tx_master doStreamReads falseset_interface_property tx_master doStreamWrites falseset_interface_property tx_master burstOnBurstBoundariesOnly falseset_interface_property tx_master ASSOCIATED_CLOCK clockadd_interface_port tx_master av_tx_readdata readdata Input 32add_interface_port tx_master av_tx_waitrequest waitrequest Input 1add_interface_port tx_master av_tx_readdatavalid readdatavalid Input 1add_interface_port tx_master av_tx_address address Output 32add_interface_port tx_master av_tx_read read Output 1# | # +-----------------------------------# +-----------------------------------# | connection point rx_master# | add_interface rx_master avalon startset_interface_property rx_master linewrapBursts falseset_interface_property rx_master adaptsTo ""set_interface_property rx_master doStreamReads falseset_interface_property rx_master doStreamWrites falseset_interface_property rx_master burstOnBurstBoundariesOnly falseset_interface_property rx_master ASSOCIATED_CLOCK clockadd_interface_port rx_master av_rx_waitrequest waitrequest Input 1add_interface_port rx_master av_rx_address address Output 32add_interface_port rx_master av_rx_write write Output 1add_interface_port rx_master av_rx_writedata writedata Output 32add_interface_port rx_master av_rx_byteenable byteenable Output 4# | # +-----------------------------------# +-----------------------------------# | connection point global# | add_interface global conduit endset_interface_property global ASSOCIATED_CLOCK clockadd_interface_port global mtx_clk_pad_i export Input 1add_interface_port global mtxd_pad_o export Output 4add_interface_port global mtxen_pad_o export Output 1add_interface_port global mtxerr_pad_o export Output 1add_interface_port global mrx_clk_pad_i export Input 1add_interface_port global mrxd_pad_i export Input 4add_interface_port global mrxdv_pad_i export Input 1add_interface_port global mrxerr_pad_i export Input 1add_interface_port global mcoll_pad_i export Input 1add_interface_port global mcrs_pad_i export Input 1add_interface_port global mdc_pad_o export Output 1add_interface_port global md_pad_i export Input 1add_interface_port global md_pad_o export Output 1add_interface_port global md_padoe_o export Output 1# | # +-----------------------------------# +-----------------------------------# | connection point control_port_irq# | add_interface control_port_irq interrupt endset_interface_property control_port_irq associatedAddressablePoint control_portset_interface_property control_port_irq ASSOCIATED_CLOCK clockadd_interface_port control_port_irq av_irq irq Output 1# | # +-----------------------------------