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-----------------------------Revision: 1.0Date: februar 18th, 2002Author: Richard Herveille- initial Verilog release----------------------------------------------------------Revision: 1.1Date: May 19th, 2002.Author: Richard Herveille- Fixed a potential bug that forced the core into an unknown state when an asynchronous reset was given without a running clock-----------------------------?? 快捷鍵說(shuō)明
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