-----------------------------Revision: 1.0Date: June 28th, 2001Author: Richard Herveille- Initial Verilog release (beta)----------------------------------------------------------Revision: 1.1Date: June 18th, 2001Author: Richard Herveille- Fixed some incomplete port lists and some Verilog related issues.  Design now completely compiles----------------------------------------------------------Revision: 1.1aDate: July 3rd, 2001Author: Richard Herveille- Rewrote some sections (controller.v, ata.v). Minor Verilog coding styles issues.----------------------------------------------------------Revision: 1.2Date: July 9th, 2001Author: Richard Herveille- added 'timescale to all files- fixed error where control registers latched data on all rising clock edges, instead of  when addressed.----------------------------------------------------------Revision: 1.3Date: July 11th, 2001Author: Richard Herveille- Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.- changed 'ata.v' into 'atahost.v'- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).----------------------------------------------------------Revision: 1.4Date: July 26th, 2001Author: Richard Herveille- Fixed some blocking versus non-blocking statement issues.----------------------------------------------------------Revision: 1.5Date: August 15th, 2001.Author: Richard Herveille- Changed filenames and top-level port names to be conform new OpenCores conventions----------------------------------------------------------Revision: 1.6Date: September 12th, 2001.Author: Richard Herveille- Made asynchronous input programmable (using atahost_define.v)----------------------------------------------------------Revision: 1.7Date: October 16th, 2001.Author: Richard Herveille- Changed programmable asynchronous level from define to parameter----------------------------------------------------------Revision: 1.8Date: Februar 16th, 2002.Author: Richard Herveille- Added disclaimer- Added CVS information- Changed core for new counter libraries- Updated testbench----------------------------------------------------------Revision: 1.9Date: Februar 17th, 2002.Author: Richard Herveille- moved wishbone interface into 'atahost_wb_slave.v'----------------------------------------------------------Revision: 1.10Date: May 19th, 2002.Author: Richard Herveille- Fixed a potential bug that forced the core into an unknown state  when an asynchronous reset was given without a running clock-----------------------------